From: lkcl Date: Sun, 3 Apr 2022 07:13:24 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~2910 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a662e1b3cf4dba5b0a65925b6e550348be3d6677;p=libreriscv.git --- diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn index 3767fc505..059bc62bb 100644 --- a/openpower/sv/branches.mdwn +++ b/openpower/sv/branches.mdwn @@ -82,14 +82,24 @@ perform needless extra tests, which will help reduce reads on the Condition Register file. *Note: Early-exit is **MANDATORY** (required) behaviour. -Branches **MUST** exit at the first failure point, for +Branches **MUST** exit at the first sequentially-encountered +failure point, for exactly the same reasons for which it is mandatory in programming languages doing early-exit: to avoid -damaging side-effects. Speculative testing of Condition +damaging side-effects and to provide deterministic +behsviour. Speculative testing of Condition Register Fields is permitted, as is speculative updating of CTR, as long as, as usual in any Out-of-Order microarchitecture, that speculative testing is cancelled should an early-exit occur.* +Also note that when early-exit occurs in Horizontal-first Mode, +srcstep, dststep etc. are all reset, ready to begin looping from the +beginning for the next instruction. However for Vertical-first +Mode srcstep etc. are incremented "as usual" i.e. the early-exit +has no special impact. This can leave srcstep etc. in an unusual +state on exit from a loop and it is up to the programmer to +reset srcstep, dststep etc. to known-good values. + Additional useful behaviour involves two primary Modes (both of which may be enabled and combined):