From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 30 Sep 2022 08:06:58 +0000 (+0100)
Subject: comments
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a67c21910a83dbd7abdcdd106c0bae2d78baf212;p=openpower-isa.git

comments
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 3a0452fc..2f212958 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -66,6 +66,9 @@ special_sprs = {
     'VRSAVE': 256}
 
 
+# rrright.  this is here basically because the compiler pywriter returns
+# results in a specific priority order.  to make sure regs match up they
+# need partial sorting. sigh.
 REG_SORT_ORDER = {
     # TODO (lkcl): adjust other registers that should be in a particular order
     # probably CA, CA32, and CR