From: Nick Clifton Date: Mon, 4 Dec 2000 23:35:10 +0000 (+0000) Subject: Fix bogons from XScale contribution X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a67ded0fdcf2ceb323d111995dafda1c73e73bca;p=gcc.git Fix bogons from XScale contribution From-SVN: r38018 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9538f2d9dbb..657a78efac9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2000-12-04 Nick Clifton + * config/arm/arm.c (arm_override_options): Test 'insn_flags' not + 'tune_flags' for XScale nature. + + * config/arm/arm.md (umulsidi3adddi): Restore "=&r" register + contraint, accidentally changed during XScale contribution. + * config/arm/lib1funcs.asm (interwork_call_via_, call_via_): Do not create these functions if the target architecture does not support Thumb instructions. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 32c772ab0ab..c5388aee442 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -526,7 +526,7 @@ arm_override_options () target_flags &= ~ARM_FLAG_APCS_FRAME; } - if (TARGET_HARD_FLOAT && (tune_flags & FL_XSCALE)) + if (TARGET_HARD_FLOAT && (insn_flags & FL_XSCALE)) { warning ("XScale does not support hardware FP instructions."); target_flags |= ARM_FLAG_SOFT_FLOAT; @@ -587,11 +587,11 @@ arm_override_options () arm_fast_multiply = (insn_flags & FL_FAST_MULT) != 0; arm_arch4 = (insn_flags & FL_ARCH4) != 0; arm_arch5 = (insn_flags & FL_ARCH5) != 0; + arm_is_xscale = (insn_flags & FL_XSCALE) != 0; arm_ld_sched = (tune_flags & FL_LDSCHED) != 0; arm_is_strong = (tune_flags & FL_STRONG) != 0; thumb_code = (TARGET_ARM == 0); - arm_is_xscale = (tune_flags & FL_XSCALE) != 0; arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32)) && !(tune_flags & FL_ARCH4))) != 0; diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 5971cfab0eb..5e5262563c2 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -1243,7 +1243,7 @@ ;; Unnamed template to match long long unsigned multiply-accumlate (umlal) (define_insn "*umulsidi3adddi" - [(set (match_operand:DI 0 "s_register_operand" "+&r") + [(set (match_operand:DI 0 "s_register_operand" "=&r") (plus:DI (mult:DI (zero_extend:DI (match_operand:SI 2 "s_register_operand" "%r"))