From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 1 Oct 2022 23:24:25 +0000 (+0100)
Subject: svstep calls SVSTATE_NEXT so needs svstate_pre_inc
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a683a43a353ef80ed79c34cb1213fb86150e1417;p=openpower-isa.git

svstep calls SVSTATE_NEXT so needs svstate_pre_inc
setvl no longer calls SVSTATE_NEXT so does not
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index c8ef0baa..c1610c4e 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1692,7 +1692,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
 
         # see if srcstep/dststep need skipping over masked-out predicate bits
         self.reset_remaps()
-        if (self.is_svp64_mode or ins_name in ['setvl', 'svstep',
+        if (self.is_svp64_mode or ins_name in ['svstep',
           'svremap', 'svstate']):
             yield from self.svstate_pre_inc()
         if self.is_svp64_mode: