From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Sun, 13 Nov 2022 18:52:23 +0000 (+0300)
Subject: power_enums: clean CR definitions
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a683e4ca2a00d417209b3c7f5ce14cacd339f54e;p=openpower-isa.git

power_enums: clean CR definitions
---

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 699c5d89..7c477b02 100644
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -403,16 +403,16 @@ class RegType(Enum):
     FRS = FPR
     FRT = FPR
 
-    CR_REG = 2  # actually CR Field. the CR register is 32-bit.
-    BF = CR_REG
-    BFA = CR_REG
+    CR_5BIT = 2 # CR field; the CR register is 32-bit
+    BF = CR_5BIT
+    BFA = CR_5BIT
 
-    CR_BIT = 3 # refers to one bit of the 32-bit CR register
-    BA = CR_BIT
-    BB = CR_BIT
-    BC = CR_BIT
-    BI = CR_BIT
-    BT = CR_BIT
+    CR_3BIT = 3 # bit of the 32-bit CR register
+    BA = CR_3BIT
+    BB = CR_3BIT
+    BC = CR_3BIT
+    BI = CR_3BIT
+    BT = CR_3BIT
 
     XER_BIT = 4   # XER bits, includes OV, OV32, SO, CA, CA32
     OV = XER_BIT
@@ -428,6 +428,11 @@ class RegType(Enum):
         return super()._missing_(value)
 
 
+class CRType(Enum):
+    CR5BIT = 0
+    CR3BIT = 1
+
+
 FPTRANS_INSNS = (
     "fatan2", "fatan2s",
     "fatan2pi", "fatan2pis",
diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index 1ec8f991..323969d3 100644
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -443,6 +443,19 @@ class SVP64Record:
     extra_reg_cr_in2 = property(_functools.partial(extra_reg, key="cr_in2"))
     extra_reg_cr_out = property(_functools.partial(extra_reg, key="cr_out"))
 
+    @property
+    def cr_3bit(self):
+        regtype = None
+        for idx in range(0, 4):
+            for entry in self.svp64.extra[idx]:
+                if entry.regtype is _SVExtraRegType.DST:
+                    if regtype is not None:
+                        raise ValueError(self.svp64)
+                    regtype = _RegType(entry.reg)
+        if regtype not in (_RegType.CR_5BIT, _RegType.CR_3BIT):
+            raise ValueError(self.svp64)
+        return (regtype is _RegType.CR_3BIT)
+
 
 class BitSel:
     def __init__(self, value=(0, 32)):
@@ -623,9 +636,9 @@ class Operands:
                         cls = GPROperand
                     elif regtype is _RegType.FPR:
                         cls = FPROperand
-                    if regtype is _RegType.CR_BIT: # 5-bit
+                    if regtype is _RegType.CR_5BIT:
                         cls = CR5Operand
-                    if regtype is _RegType.CR_REG: # actually CR Field, 3-bit
+                    if regtype is _RegType.CR_3BIT:
                         cls = CR3Operand
 
                 mapping[name] = (cls, {"name": name})
@@ -1255,7 +1268,7 @@ class ConditionRegisterFieldOperand(ExtendableOperand):
     XCR = fr"{CR}\.{BIT}"
     PATTERNS = tuple(map(pattern, (
         ("CR", CR),
-        ("CR_BIT", XCR),
+        ("XCR", XCR),
         ("CR*N", CRN),
         ("N*CR", NCR),
         ("BIT+CR", (LBIT + CR)),
@@ -1267,7 +1280,7 @@ class ConditionRegisterFieldOperand(ExtendableOperand):
     )))
 
     def remap(self, value, vector, regtype):
-        if regtype is _RegType.CR_BIT:
+        if regtype is _RegType.CR_5BIT:
             subvalue = (value & 0x3)
             value >>= 2
 
@@ -1297,7 +1310,7 @@ class ConditionRegisterFieldOperand(ExtendableOperand):
                     "scalar CR cannot fit into EXTRA3"
                 extra &= 0x3
 
-        if regtype is _RegType.CR_BIT:
+        if regtype is _RegType.CR_5BIT:
             value = ((value << 2) | subvalue)
 
         return (value, extra)
@@ -1319,7 +1332,7 @@ class ConditionRegisterFieldOperand(ExtendableOperand):
                     values = match.groups()
                     match = dict(zip(keys, values))
                     CR = int(match["CR"])
-                    if name == "CR_BIT":
+                    if name == "XCR":
                         N = 4
                     else:
                         N = int(match.get("N", "1"))
@@ -1366,14 +1379,14 @@ class ConditionRegisterFieldOperand(ExtendableOperand):
 class CR3Operand(ConditionRegisterFieldOperand):
     def remap(self, value, vector):
         return super().remap(value=value, vector=vector,
-            regtype=_RegType.CR_REG)
+            regtype=_RegType.CR_3BIT)
 
 
 @_dataclasses.dataclass(eq=True, frozen=True)
 class CR5Operand(ConditionRegisterFieldOperand):
     def remap(self, value, vector):
         return super().remap(value=value, vector=vector,
-            regtype=_RegType.CR_BIT)
+            regtype=_RegType.CR_5BIT)
 
     def sv_spec_enter(self, value, span):
         value = _SelectableInt(value=(value.value >> 2), bits=3)
@@ -2394,26 +2407,11 @@ class RM(BaseRM):
             table = (
                 (0b000000, 0b111000, "simple"), # simple
                 (0b001000, 0b111000, "mr"),     # mapreduce
-                (0b100001, 0b100001, "ff3"),    # failfirst, 3-bit CR
-                (0b100000, 0b100000, "ff5"),    # failfirst, 5-bit CR
+                (0b100001, 0b100001, "ff3"),    # ffirst, 3-bit CR
+                (0b100000, 0b100000, "ff5"),    # ffirst, 5-bit CR
             )
-            # determine CR type, 5-bit (BA/BB/BT) or 3-bit Field (BF/BFA)
-            regtype = None
-            for idx in range(0, 4):
-                for entry in record.svp64.extra[idx]:
-                    if entry.regtype is _SVExtraRegType.DST:
-                        if regtype is not None:
-                            raise ValueError(record.svp64)
-                        regtype = _RegType(entry.reg)
-            if regtype is _RegType.CR_REG:
-                regtype = 0 # 5-bit
-            elif regtype is _RegType.CR_BIT:
-                regtype = 1 # 3-bit
-            else:
-                raise ValueError(record.svp64)
-            # finally provide info for search
             rm = rm.cr_op
-            search = ((int(rm.mode) << 1) | (regtype or 0))
+            search = ((int(rm.mode) << 1) | int(record.svp64.cr_3bit))
 
         elif record.svp64.mode is _SVMode.BRANCH:
             # just mode 2-bit