From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 31 Jan 2022 08:38:25 +0000 (+0100)
Subject: Use edges when explicit
X-Git-Tag: yosys-0.14~2^2~13
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a6959d30df067c27da75d12bc0bd5233eb91d3ca;p=yosys.git

Use edges when explicit
---

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index e67f8246b..ff815b69a 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -74,6 +74,7 @@ struct SimShared
 	double start_time = 0;
 	double stop_time = -1;
 	SimulationMode sim_mode = SimulationMode::cmp;
+	bool cycles_set = false;
 };
 
 void zinit(State &v)
@@ -1016,7 +1017,9 @@ struct SimWorker : SimShared
 			log_error("Stop time is before start time\n");
 		}
 		auto edges = fst->getAllEdges(fst_clock, startCount, stopCount);
-		
+		if (cycles_set && ((size_t)(numcycles *2) < edges.size()))
+			edges.erase(edges.begin() + (numcycles*2), edges.end());
+
 		if ((startCount == stopCount) && writeback) {
 			log("Update initial state with values from %zu\n",startCount);
 			if (edges.empty())
@@ -1143,6 +1146,7 @@ struct SimPass : public Pass {
 			}
 			if (args[argidx] == "-n" && argidx+1 < args.size()) {
 				numcycles = atoi(args[++argidx].c_str());
+				worker.cycles_set = true;
 				continue;
 			}
 			if (args[argidx] == "-rstlen" && argidx+1 < args.size()) {