From: Luke Kenneth Casson Leighton Date: Sat, 31 Aug 2019 08:01:29 +0000 (+0100) Subject: whitespace X-Git-Tag: convert-csv-opcode-to-binary~4182 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a69a4920b86a4d41d3e6444383dd1bb9097c760a;p=libreriscv.git whitespace --- diff --git a/simple_v_extension/specification/sv.setvl.mdwn b/simple_v_extension/specification/sv.setvl.mdwn index be7db76a9..80d6296c5 100644 --- a/simple_v_extension/specification/sv.setvl.mdwn +++ b/simple_v_extension/specification/sv.setvl.mdwn @@ -1,9 +1,12 @@ # SV setvl -sv.setvl allows optional setting of both MVL and of indirectly marking one of the scalar registers as being VL. +sv.setvl allows optional setting of both MVL and of indirectly marking +one of the scalar registers as being VL. -Unlike the majority of other CSRs, which contain status bits that change behaviour, VL is closely interlinked with the instructions it affects and often requires arithmetic interaction. -Thus it makes more sense to actually *use* one of the scalar registers *as* VL. +Unlike the majority of other CSRs, which contain status bits that change +behaviour, VL is closely interlinked with the instructions it affects +and often requires arithmetic interaction. Thus it makes more sense to +actually *use* one of the scalar registers *as* VL. Format for Vector Configuration Instructions under OP-V major opcode: