From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 19 Feb 2022 15:54:05 +0000 (+0000)
Subject: match up dram initialisation parameters
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a6b2652007b96a93a7a9baee18c8131fab64e23c;p=ls2.git

match up dram initialisation parameters
---

diff --git a/Makefile b/Makefile
index b547e2e..0943765 100644
--- a/Makefile
+++ b/Makefile
@@ -27,6 +27,7 @@ endif
 # Hello world
 MEMORY_SIZE=8192
 RAM_INIT_FILE=hello_world/hello_world.bin
+RAM_INIT_FILE=coldboot/coldboot.bin
 SIM_MAIN_BRAM=false
 
 # Micropython
diff --git a/coldboot/coldboot.c b/coldboot/coldboot.c
index 3026442..8eba6a1 100644
--- a/coldboot/coldboot.c
+++ b/coldboot/coldboot.c
@@ -2,6 +2,7 @@
 #include <stdbool.h>
 
 #include "console.h"
+#include "microwatt_soc.h"
 
 #include <stdlib.h>
 #include <stdint.h>
@@ -74,9 +75,9 @@ int main(void) {
 		.rdly_p1 = 2,
 	};
 	struct gramProfile profile2;
-	gram_init(&ctx, &profile, (void*)0x10000000,
-                              (void*)0x00009000, 
-                              (void*)0x00008000);
+	gram_init(&ctx, &profile, (void*)DRAM_BASE, //0x10000000,
+                              (void*)DRAM_CTRL_BASE, //0x00009000,
+                              (void*)DRAM_INIT_BASE); //0x00008000);
 	puts("done\n");
 
 	puts("Rdly\np0: ");
diff --git a/src/ls2.py b/src/ls2.py
index 6486bdd..2d5807f 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -298,9 +298,10 @@ if __name__ == "__main__":
 
     # set up the SOC
     soc = DDR3SoC(dram_cls=dram_cls,
-                  ddrphy_addr=0xff000000, # DRAM firmware init base
-                  dramcore_addr=0x80000000,
-                  ddr_addr=0x10000000,
+                  # check microwatt_soc.h for these
+                  ddrphy_addr=0xff000000,   # DRAM_INIT_BASE firmware base
+                  dramcore_addr=0xc8000000, # DRAM_CTRL_BASE
+                  ddr_addr=0x40000000,      # DRAM_BASE
                   fw_addr=fw_addr,
                   #fw_addr=None,
                   ddr_pins=ddr_pins,