From: lkcl <lkcl@web>
Date: Sun, 6 Dec 2020 14:45:01 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1496
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a6ba5821389110b29f2f71f1269ecf4d31c6555b;p=libreriscv.git

---

diff --git a/resources.mdwn b/resources.mdwn
index 8ee3dc6a3..3bf9fc29f 100644
--- a/resources.mdwn
+++ b/resources.mdwn
@@ -68,9 +68,10 @@ most software as-is and avoid major forks.
 * [RISC-V Supervisor Binary Interface Specification](https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md)
 
 Note: As far as I know, we aren't using the RISC-V V Extension directly
-at the moment. However, there are many wiki pages that make a reference
+at the moment (correction: we were never going to). However, there are many wiki pages that make a reference
 to the V extension so it would be good to include it here as a reference
 for comparative/informative purposes with regard to Simple-V.
+<https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vsetvlivsetvl-instructions>
 
 # Radix MMU
  - [Qemu emulation](https://github.com/qemu/qemu/commit/d5fee0bbe68d5e61e2d2beb5ff6de0b9c1cfd182)