From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 6 Aug 2019 23:23:37 +0000 (-0700)
Subject: RTLIL::S{0,1} -> State::S{0,1}
X-Git-Tag: working-ls180~1151^2~12
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a6bc9265fbb2abad73120a068a09f0c7833304de;p=yosys.git

RTLIL::S{0,1} -> State::S{0,1}
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index a3a753912..615854459 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -388,11 +388,11 @@ struct XAigerWriter
 						RTLIL::SigSpec rhs;
 						if (it != cell->connections_.end()) {
 							if (GetSize(it->second) < GetSize(w))
-								it->second.append(RTLIL::SigSpec(RTLIL::S0, GetSize(w)-GetSize(it->second)));
+								it->second.append(RTLIL::SigSpec(State::S0, GetSize(w)-GetSize(it->second)));
 							rhs = it->second;
 						}
 						else {
-							rhs = RTLIL::SigSpec(RTLIL::S0, GetSize(w));
+							rhs = RTLIL::SigSpec(State::S0, GetSize(w));
 							cell->setPort(port_name, rhs);
 						}
 
@@ -400,10 +400,10 @@ struct XAigerWriter
 						for (auto b : rhs.bits()) {
 							SigBit I = sigmap(b);
 							if (b == RTLIL::Sx)
-								b = RTLIL::S0;
+								b = State::S0;
 							else if (I != b) {
 								if (I == RTLIL::Sx)
-									alias_map[b] = RTLIL::S0;
+									alias_map[b] = State::S0;
 								else
 									alias_map[b] = I;
 							}
@@ -672,7 +672,7 @@ struct XAigerWriter
 							if (holes_cell)
 								port_wire.append(holes_wire);
 							else
-								holes_module->connect(holes_wire, RTLIL::S0);
+								holes_module->connect(holes_wire, State::S0);
 						}
 						if (!port_wire.empty())
 							holes_cell->setPort(w->name, port_wire);
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index bb97c5703..4ecd01993 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -151,12 +151,12 @@ struct ConstEvalAig
 
 		RTLIL::State eval_ret = RTLIL::Sx;
 		if (cell->type == "$_NOT_") {
-			if (sig_a == RTLIL::S0) eval_ret = RTLIL::S1;
-			else if (sig_a == RTLIL::S1) eval_ret = RTLIL::S0;
+			if (sig_a == State::S0) eval_ret = State::S1;
+			else if (sig_a == State::S1) eval_ret = State::S0;
 		}
 		else if (cell->type == "$_AND_") {
-			if (sig_a == RTLIL::S0) {
-				eval_ret = RTLIL::S0;
+			if (sig_a == State::S0) {
+				eval_ret = State::S0;
 				goto eval_end;
 			}
 
@@ -164,15 +164,15 @@ struct ConstEvalAig
 				RTLIL::SigBit sig_b = cell->getPort("\\B");
 				if (!eval(sig_b))
 					return false;
-				if (sig_b == RTLIL::S0) {
-					eval_ret = RTLIL::S0;
+				if (sig_b == State::S0) {
+					eval_ret = State::S0;
 					goto eval_end;
 				}
 
-				if (sig_a != RTLIL::S1 || sig_b != RTLIL::S1)
+				if (sig_a != State::S1 || sig_b != State::S1)
 					goto eval_end;
 
-				eval_ret = RTLIL::S1;
+				eval_ret = State::S1;
 			}
 		}
 		else log_abort();
@@ -256,7 +256,7 @@ end_of_header:
 
 	RTLIL::Wire* n0 = module->wire("\\__0__");
 	if (n0)
-		module->connect(n0, RTLIL::S0);
+		module->connect(n0, State::S0);
 
 	// Parse footer (symbol table, comments, etc.)
 	unsigned l1;
@@ -371,7 +371,7 @@ void AigerReader::parse_xaiger()
 
 	RTLIL::Wire* n0 = module->wire("\\__0__");
 	if (n0)
-		module->connect(n0, RTLIL::S0);
+		module->connect(n0, State::S0);
 
 	dict<int,IdString> box_lookup;
 	for (auto m : design->modules()) {
@@ -535,9 +535,9 @@ void AigerReader::parse_aiger_ascii()
 				log_error("Line %u cannot be interpreted as a latch!\n", line_count);
 
 			if (l3 == 0)
-				q_wire->attributes["\\init"] = RTLIL::S0;
+				q_wire->attributes["\\init"] = State::S0;
 			else if (l3 == 1)
-				q_wire->attributes["\\init"] = RTLIL::S1;
+				q_wire->attributes["\\init"] = State::S1;
 			else if (l3 == l1) {
 				//q_wire->attributes["\\init"] = RTLIL::Sx;
 			}
@@ -546,7 +546,7 @@ void AigerReader::parse_aiger_ascii()
 		}
 		else {
 			// AIGER latches are assumed to be initialized to zero
-			q_wire->attributes["\\init"] = RTLIL::S0;
+			q_wire->attributes["\\init"] = State::S0;
 		}
 		latches.push_back(q_wire);
 	}
@@ -660,9 +660,9 @@ void AigerReader::parse_aiger_binary()
 				log_error("Line %u cannot be interpreted as a latch!\n", line_count);
 
 			if (l3 == 0)
-				q_wire->attributes["\\init"] = RTLIL::S0;
+				q_wire->attributes["\\init"] = State::S0;
 			else if (l3 == 1)
-				q_wire->attributes["\\init"] = RTLIL::S1;
+				q_wire->attributes["\\init"] = State::S1;
 			else if (l3 == l1) {
 				//q_wire->attributes["\\init"] = RTLIL::Sx;
 			}
@@ -671,7 +671,7 @@ void AigerReader::parse_aiger_binary()
 		}
 		else {
 			// AIGER latches are assumed to be initialized to zero
-			q_wire->attributes["\\init"] = RTLIL::S0;
+			q_wire->attributes["\\init"] = State::S0;
 		}
 		latches.push_back(q_wire);
 	}