From: Luke Kenneth Casson Leighton Date: Sun, 11 Sep 2022 18:51:41 +0000 (+0100) Subject: change to Extension X-Git-Tag: opf_rfc_ls005_v1~488 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a6be32bacb12e244eb814f21b41cfe7c240fdfd5;p=libreriscv.git change to Extension --- diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index ba519ba78..5ce770f0c 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -61,17 +61,17 @@ capability present in every Commercial 3D GPU ISA, but it is the *Vectorised* Branch-Conditional that is augmented, not Scalar Branch. -# Compliancy Levels +# Extension Levels Simple-V has been subdivided into levels akin to the Power ISA Compliancy -Levels. For now let us call them "SV Compliancy Levels" to differentiate +Levels. For now let us call them "SV Extension Levels" to differentiate the two. The reason for the -[SV Compliancy Levels](https://libre-soc.org/openpower/sv/compliancy_levels/) +[SV Extension Levels](https://libre-soc.org/openpower/sv/compliancy_levels/) is the same as for the Power ISA Compliancy Levels (SFFS, SFS): to not overburden implementors with features that they do not need. *There is no dependence between -the two types of Compliancy Levels*. The resources below therefore are -not all required for all SV Compliancy Levels but they are all required +the two types of Levels*. The resources below therefore are +not all required for all SV Extension Levels but they are all required to be reserved. # Binary Interoperability @@ -104,7 +104,7 @@ practical to implement on an extremely wide range of Industry-wide common **Scalar** micro-architectures. Finite State Machine (for ultra-low-resource and Mission-Critical), In-order single-issue, all the way through to Great-Big Out-of-Order Superscalar Multi-Issue. The -SV Compliancy Levels specifically recognise these differing scenarios. +SV Extension Levels specifically recognise these differing scenarios. SIMD back-end ALUs particularly those with element-level predicate masks may be exploited to good effect with very little additional @@ -114,7 +114,7 @@ limitations extend also to when Simple-V is deployed, which is why Multi-Issue Out-of-Order is the recommended (but not mandatory) Scalar Micro-architecture. -The only major concern is in the upper SV Compliancy Levels: the Hazard +The only major concern is in the upper SV Extension Levels: the Hazard Management for increased number of Scalar Registers to 128 (in current versions) but given that IBM POWER9/10 has VSX register numbering 64, and modern GPUs have 128, 256 amd even 512 registers this was deemed