From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 2 Mar 2017 15:39:48 +0000 (+0100)
Subject: Add write_aiger $anyseq support
X-Git-Tag: yosys-0.8~461
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a6ca28276e3786ba3d756f46d7804a6dcf1e5b11;p=yosys.git

Add write_aiger $anyseq support
---

diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc
index 02871a6fd..5bc268437 100644
--- a/backends/aiger/aiger.cc
+++ b/backends/aiger/aiger.cc
@@ -188,6 +188,13 @@ struct AigerWriter
 				continue;
 			}
 
+			if (cell->type == "$anyseq")
+			{
+				for (auto bit : sigmap(cell->getPort("\\Y")))
+					input_bits.insert(bit);
+				continue;
+			}
+
 			log_error("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
 		}