From: lkcl <lkcl@web>
Date: Mon, 8 May 2023 11:42:00 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a6ce9b08348c36c1157d37f93bf457ba3135f847;p=libreriscv.git

---

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 902bd73c2..63f23149a 100644
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -75,7 +75,7 @@ Field result *is* the main result.
 
 SVP64 RM `MODE` (includes `ELWIDTH_SRC` bits) for CR-based operations:
 
-|6 | 7 |19-20|21 | 22   23 |  description     |
+|6 | 7 |19:20|21 | 22:23   |  description     |
 |--|---|-----|---|---------|------------------|
 |/ | / |0 RG | 0 | dz  sz  | simple mode                      |
 |/ | / |0 RG | 1 | dz  sz  | scalar reduce mode (mapreduce) |