From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 25 Oct 2021 13:19:02 +0000 (+0100)
Subject: debugging of initial test_partsig_scope.py mini-test
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a6d8cf59913a282a209d8ee4648003da454af3d2;p=ieee754fpu.git

debugging of initial test_partsig_scope.py mini-test
scope and shape need to be stored in SimdSignal in order to get at them
later
---

diff --git a/src/ieee754/part/partsig.py b/src/ieee754/part/partsig.py
index 343aca58..26e526ac 100644
--- a/src/ieee754/part/partsig.py
+++ b/src/ieee754/part/partsig.py
@@ -94,13 +94,13 @@ class ElwidPartType:  # TODO decide name
         self.psig = psig
 
     def get_mask(self):
-        return self.psig.shape.partpoints.values()  # i think
+        return list(self.psig._shape.partpoints.values())  # i think
 
     def get_switch(self):
         return self.psig.scope.elwid       # switch on elwid: match get_cases()
 
     def get_cases(self):
-        return self.psig.shape.bitp.keys() # all possible values of elwid
+        return self.psig._shape.bitp.keys() # all possible values of elwid
 
     @property
     def blanklanes(self):
@@ -119,8 +119,9 @@ class SimdShape(Shape):
                               signed=False,
                               fixed_width=None): # fixed overall width
         widths_at_elwid = width
+        print ("SimdShape width", width, "fixed_width", fixed_width)
         # this check is done inside layout but do it again here anyway
-        assert fixed_width == None and widths_at_elwid == None, \
+        assert fixed_width != None or widths_at_elwid != None, \
             "both width (widths_at_elwid) and fixed_width cannot be None"
         (pp, bitp, lpoints, bmask, fixed_width, lane_shapes, part_wid) = \
             layout(scope.elwid,
@@ -128,10 +129,10 @@ class SimdShape(Shape):
                    widths_at_elwid,
                    fixed_width)
         self.partpoints = pp
-        self.bitp = bitp       # binary values for partpoints at each elwidth
-        self.lpoints = lpoints # layout ranges
-        self.blankmask = bmask # blanking mask (partitions always padding)
-        self.partwid = partwid # smallest alignment start point for elements
+        self.bitp = bitp        # binary values for partpoints at each elwidth
+        self.lpoints = lpoints  # layout ranges
+        self.blankmask = bmask  # blanking mask (partitions always padding)
+        self.partwid = part_wid # smallest alignment start point for elements
 
         # pass through the calculated width to Shape() so that when/if
         # objects using this Shape are downcast, they know exactly how to
@@ -145,15 +146,18 @@ class SimdSignal(UserValue):
     # XXX ################################################### XXX
     def __init__(self, mask, shape=None, *args, src_loc_at=0, **kwargs):
         super().__init__(src_loc_at=src_loc_at)
+        print ("SimdSignal shape", shape)
         # create partition points
         if isinstance(mask, SimdScope): # mask parameter is a SimdScope
+            self.scope = mask
             self.ptype = ElwidPartType(self)
             # adapt shape to a SimdShape
             if not isinstance(shape, SimdShape):
-                shape = SimdShape(mask, shape)
+                shape = SimdShape(self.scope, shape)
+            self._shape = shape
             self.sig = Signal(shape, *args, **kwargs)
             # get partpoints from SimdShape
-            self.partpoints = ptype.partpoints
+            self.partpoints = shape.partpoints
         else:
             self.sig = Signal(shape, *args, **kwargs)
             width = len(self.sig)  # get signal width
diff --git a/src/ieee754/part/simd_scope.py b/src/ieee754/part/simd_scope.py
index 28d1782e..057901b3 100644
--- a/src/ieee754/part/simd_scope.py
+++ b/src/ieee754/part/simd_scope.py
@@ -131,6 +131,7 @@ class SimdScope:
             # set the module context so that the SimdSignal can create
             # its own submodules during AST creation
             s.set_module(self.module)
+            return s
 
     # XXX TODO
     def Signal_like(self): pass
diff --git a/src/ieee754/part/test/test_partsig_scope.py b/src/ieee754/part/test/test_partsig_scope.py
index 19ae9560..09aab823 100644
--- a/src/ieee754/part/test/test_partsig_scope.py
+++ b/src/ieee754/part/test/test_partsig_scope.py
@@ -37,7 +37,7 @@ class TestCatMod(Elaboratable):
         self.cat_out = self.o.sig
 
     def elaborate(self, platform):
-        m = Module()
+        m = self.m
         comb = m.d.comb
 
         comb += self.o.eq(Cat(self.a, self.b))