From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 11 Jun 2020 10:53:00 +0000 (+0100)
Subject: yield needed for unit tests to work (has to go)
X-Git-Tag: div_pipeline~398
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a6eab3962ac143f0716bab896f5331808d56cf56;p=soc.git

yield needed for unit tests to work (has to go)
---

diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py
index a62a4694..ee3c6fce 100644
--- a/src/soc/fu/compunits/test/test_compunit.py
+++ b/src/soc/fu/compunits/test/test_compunit.py
@@ -199,12 +199,12 @@ class TestRunner(FHDLTestCase):
                     wr_rel_o = yield cu.wr.rel
                     print ("before inputs, rd_rel, wr_rel: ",
                             bin(rd_rel_o), bin(wr_rel_o))
-                    yield
                     assert wr_rel_o == 0, "wr.rel %s must be zero. "\
                                 "previous instr not written all regs\n"\
                                 "respec %s" % \
                                 (bin(wr_rel_o), cu.rwid[1])
                     yield from set_cu_inputs(cu, inp)
+                    yield
                     rd_rel_o = yield cu.rd.rel
                     wr_rel_o = yield cu.wr.rel
                     wrmask = yield cu.wrmask
@@ -219,6 +219,11 @@ class TestRunner(FHDLTestCase):
                     yield Settle()
                     # get all outputs (one by one, just "because")
                     res = yield from get_cu_outputs(cu, code)
+                    wrmask = yield cu.wrmask
+                    rd_rel_o = yield cu.rd.rel
+                    wr_rel_o = yield cu.wr.rel
+                    print ("after got outputs, rd_rel, wr_rel, wrmask: ",
+                            bin(rd_rel_o), bin(wr_rel_o), bin(wrmask))
 
                     # wait for busy to go low
                     while True: