From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 30 Apr 2019 00:04:46 +0000 (+0100)
Subject: make _connect_in/_connect_out data eq optional
X-Git-Tag: ls180-24jan2020~1103
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a6eb987d7e92f20012eb8eccfa6d0f59f97a9031;p=ieee754fpu.git

make _connect_in/_connect_out data eq optional
---

diff --git a/src/add/iocontrol.py b/src/add/iocontrol.py
index 14d2730e..f9d15bd2 100644
--- a/src/add/iocontrol.py
+++ b/src/add/iocontrol.py
@@ -188,16 +188,17 @@ class PrevControl(Elaboratable):
             return self.s_ready_o # set dynamically by stage
         return self._ready_o      # return this when not under dynamic control
 
-    def _connect_in(self, prev, direct=False, fn=None):
+    def _connect_in(self, prev, direct=False, fn=None, do_data=True):
         """ internal helper function to connect stage to an input source.
             do not use to connect stage-to-stage!
         """
         valid_i = prev.valid_i if direct else prev.valid_i_test
+        res = [self.valid_i.eq(valid_i),
+               prev.ready_o.eq(self.ready_o)]
+        if do_data is False:
+            return res
         data_i = fn(prev.data_i) if fn is not None else prev.data_i
-        return [self.valid_i.eq(valid_i),
-                prev.ready_o.eq(self.ready_o),
-                nmoperator.eq(self.data_i, data_i),
-               ]
+        return res + [nmoperator.eq(self.data_i, data_i)]
 
     @property
     def valid_i_test(self):
diff --git a/src/add/test_fsm_experiment.py b/src/add/test_fsm_experiment.py
index d9c76e60..0e820c96 100644
--- a/src/add/test_fsm_experiment.py
+++ b/src/add/test_fsm_experiment.py
@@ -100,11 +100,8 @@ class FPDIVPipe(ControlBase):
         m.submodules.fpdiv = self.fpdiv
 
         # see if connecting to stb/ack works
-        m.d.comb += self.p.ready_o.eq(self.fpdiv.in_a.ready_o)
-        m.d.comb += self.fpdiv.in_a.valid_i.eq(self.p.valid_i_test)
-
-        m.d.comb += self.n.valid_o.eq(self.fpdiv.out_z.valid_o)
-        m.d.comb += self.fpdiv.out_z.ready_i.eq(self.n.ready_i_test)
+        m.d.comb += self.fpdiv.in_a._connect_in(self.p)
+        m.d.comb += self.fpdiv.out_z._connect_out(self.n, do_data=False)
         m.d.comb += self.n.data_o.eq(self.data_r)
 
         return m