From: lkcl <lkcl@web>
Date: Sat, 21 Nov 2020 21:30:19 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1700
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a6ebae75f23de3bacf1067c1388d747c3c4f578d;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index 7f8f25373..a92855ecb 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -16,6 +16,9 @@ Advantages of these design principles:
 * It is therefore easy to create a first (and sometimes only) implementation as literally a for-loop in hardware, simulators, and compilers.
 * More complex HDL can be done by repeating existing scalar ALUs and pipelines as blocks.
 * As (mostly) a high-level "context" that does not (significantly) deviate from scalar OpenPOWER ISA and, in its purest form being "a for loop around scalar instructions", it is minimally-disruptive and consequently stands a reasonable chance of broad community adoption and acceptance
+* Completely wipes not just SIMD opcode proliferation off the
+  map but off of Vectorisation as well.  No more separate Vector
+  instructions.
 
 Pages being developed and examples