From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 23 May 2022 17:13:45 +0000 (+0200)
Subject: Use analysis mode if set in file
X-Git-Tag: divfloor-in-write_smt2-old-test~4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a6ec5754c6c2be6877904569b644ad8eae4aac1c;p=yosys.git

Use analysis mode if set in file
---

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index b130edbdc..29131fdc5 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -2717,7 +2717,7 @@ struct VerificPass : public Pass {
 
 		if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F"))
 		{
-			unsigned verilog_mode = veri_file::VERILOG_95; // default recommended by Verific
+			unsigned verilog_mode = veri_file::UNDEFINED;
 			bool is_formal = false;
 			const char* filename = nullptr;
 
@@ -2764,7 +2764,7 @@ struct VerificPass : public Pass {
 			veri_file::DefineMacro("VERIFIC");
 			veri_file::DefineMacro(is_formal ? "FORMAL" : "SYNTHESIS");
 
-			if (!veri_file::AnalyzeMultipleFiles(file_names, verilog_mode, work.c_str(), veri_file::MFCU)) {
+			if (!veri_file::AnalyzeMultipleFiles(file_names, analysis_mode, work.c_str(), veri_file::MFCU)) {
 				verific_error_msg.clear();
 				log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n");
 			}