From: Ali Saidi <saidi@eecs.umich.edu>
Date: Mon, 22 Jan 2007 01:02:41 +0000 (-0500)
Subject: make sure that page bits of VA on tlb insert are 0
X-Git-Tag: m5_2.0_beta3~224^2~9^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a7072c19dbd6273920a90a4ec5fa013531316287;p=gem5.git

make sure that page bits of VA on tlb insert are 0

--HG--
extra : convert_revision : f04af884687e9b8631e910cf62cd4a58d035c744
---

diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 460a9c640..61445954f 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -85,6 +85,7 @@ TLB::insert(Addr va, int partition_id, int context_id, bool real,
     int x;
 
     cacheValid = false;
+    va &= ~(PTE.size()-1);
  /*   tr.va = va;
     tr.size = PTE.size() - 1;
     tr.contextId = context_id;