From: Lisa Hsu <Lisa.Hsu@amd.com>
Date: Thu, 25 Feb 2010 18:13:40 +0000 (-0800)
Subject: configs: pull out cache configuration code from se.py and fs.py.
X-Git-Tag: stable_2012_02_02~1501
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a70f70ccbff28e80f247507204fa3d1eff8b1baf;p=gem5.git

configs: pull out cache configuration code from se.py and fs.py.
Most of these frontend configurations share cache configuration code, pull it out so that
changes to caches don't have to require changing multiple config files.
---

diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
new file mode 100644
index 000000000..075f6d235
--- /dev/null
+++ b/configs/common/CacheConfig.py
@@ -0,0 +1,53 @@
+# Copyright (c) 2010 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Lisa Hsu
+
+# Configure the M5 cache hierarchy config in one place
+#
+
+import m5
+from m5.objects import *
+from Caches import *
+
+def config_cache(options, system):
+    if options.l2cache:
+        system.l2 = L2Cache(size='2MB')
+        system.tol2bus = Bus()
+        system.l2.cpu_side = system.tol2bus.port
+        system.l2.mem_side = system.membus.port
+        system.l2.num_cpus = options.num_cpus
+
+    for i in xrange(options.num_cpus):
+        if options.caches:
+            system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
+                                                  L1Cache(size = '64kB'))
+        if options.l2cache:
+            system.cpu[i].connectMemPorts(system.tol2bus)
+        else:
+            system.cpu[i].connectMemPorts(system.membus)
+
+    return system
diff --git a/configs/example/fs.py b/configs/example/fs.py
index 23285e101..c0b434eb3 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -44,6 +44,7 @@ from FSConfig import *
 from SysPaths import *
 from Benchmarks import *
 import Simulation
+import CacheConfig
 from Caches import *
 
 # Get paths we might need.  It's expected this file is in m5/configs/example.
@@ -120,11 +121,7 @@ if options.kernel is not None:
 if options.script is not None:
     test_sys.readfile = options.script
 
-if options.l2cache:
-    test_sys.l2 = L2Cache(size = '2MB')
-    test_sys.tol2bus = Bus()
-    test_sys.l2.cpu_side = test_sys.tol2bus.port
-    test_sys.l2.mem_side = test_sys.membus.port
+CacheConfig.config_cache(options, system)
 
 test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
 
@@ -136,14 +133,6 @@ if options.caches or options.l2cache:
     test_sys.iocache.mem_side = test_sys.membus.port
 
 for i in xrange(np):
-    if options.caches:
-        test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
-                                                L1Cache(size = '64kB'))
-    if options.l2cache:
-        test_sys.cpu[i].connectMemPorts(test_sys.tol2bus)
-    else:
-        test_sys.cpu[i].connectMemPorts(test_sys.membus)
-
     if options.fastmem:
         test_sys.cpu[i].physmem_port = test_sys.physmem.port
 
diff --git a/configs/example/se.py b/configs/example/se.py
index 7c09bcc5c..a249f46dd 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -46,6 +46,7 @@ if buildEnv['FULL_SYSTEM']:
 addToPath('../common')
 
 import Simulation
+import CacheConfig
 from Caches import *
 from cpu2000 import *
 
@@ -146,21 +147,9 @@ system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
 
 system.physmem.port = system.membus.port
 
-if options.l2cache:
-    system.l2 = L2Cache(size='2MB')
-    system.tol2bus = Bus()
-    system.l2.cpu_side = system.tol2bus.port
-    system.l2.mem_side = system.membus.port
-    system.l2.num_cpus = np
+CacheConfig.config_cache(options, system)
 
 for i in xrange(np):
-    if options.caches:
-        system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
-                                              L1Cache(size = '64kB'))
-    if options.l2cache:
-        system.cpu[i].connectMemPorts(system.tol2bus)
-    else:
-        system.cpu[i].connectMemPorts(system.membus)
     system.cpu[i].workload = process
 
     if options.fastmem: