From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 7 Jan 2022 12:26:45 +0000 (+0000)
Subject: add msr_o to issuer in microwatt_compat mode
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a71b3a372cea37a75eb575e94fc116033901c711;p=soc.git

add msr_o to issuer in microwatt_compat mode
---

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index cbf6cf2b..7f1ae097 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -326,6 +326,7 @@ class TestIssuerBase(Elaboratable):
         # this is for verilator debug purposes
         if self.microwatt_compat:
             self.nia = Signal(64)
+            self.msr_o = Signal(64)
             self.nia_req = Signal(1)
             self.insn = Signal(32)
 
@@ -683,7 +684,7 @@ class TestIssuerBase(Elaboratable):
             ports = [self.core.o.core_terminate_o,
                      self.ext_irq,
                      self.alt_reset, # not connected yet
-                     self.nia, self.insn, self.nia_req,
+                     self.nia, self.insn, self.nia_req, self.msr_o,
                      ClockSignal(),
                      ResetSignal(),
                     ]
@@ -855,6 +856,7 @@ class TestIssuerInternal(TestIssuerBase):
                                 # for verilator debug purposes
                                 comb += self.insn.eq(insn)
                                 comb += self.nia.eq(cur_state.pc)
+                                comb += self.msr_o.eq(cur_state.msr)
                                 comb += self.nia_req.eq(1)
                             m.next = "INSN_READY"