From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 12 Apr 2021 18:27:51 +0000 (+0000)
Subject: enable HFNS in adder
X-Git-Tag: LS180_RC3~123
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a72e23db6f1fb81d260a741be152724abf975370;p=soclayout.git

enable HFNS in adder
---

diff --git a/experiments10_verilog/freepdk_c4m45/doDesign.py b/experiments10_verilog/freepdk_c4m45/doDesign.py
index 4acedc7..3de3798 100644
--- a/experiments10_verilog/freepdk_c4m45/doDesign.py
+++ b/experiments10_verilog/freepdk_c4m45/doDesign.py
@@ -84,7 +84,7 @@ def scriptMain ( **kw ):
         adderConf.editor = editor
         adderConf.useSpares = True
         adderConf.useClockTree = True
-        #adderConf.useHFNS = True
+        adderConf.useHFNS = True
         adderConf.bColumns = 2
         adderConf.bRows = 2
         adderConf.chipConf.name = 'chip'