From: lkcl <lkcl@web>
Date: Sat, 18 Jun 2022 13:54:27 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1706
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a732f573ffd13c1ab49bc9f4f50695576767b4f7;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index 57eb3f0fc..7779f1f78 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -69,7 +69,7 @@ Comparative instruction count:
 * ARM SVE2: around 1,000 instructions, prerequisite: SVE
 * Intel AVX-512: around 4,000 instructions, prerequisite AVX2 etc.
 * RISV-V RVV: 192 instructions, prerequisite 96 Scalar RV64GC instructions
-* SVP64: **four** instructions, 24-bit prefixing of
+* SVP64: **five** instructions, 24-bit prefixing of
   prerequisite SFS (150) or
   SFFS (214) Compliancy Subsets
 
@@ -112,7 +112,7 @@ Core SVP64 instructions:
 
 *Please note: there are only five instructions in the whole of SV.
 Beyond this point are additional **Scalar** instructions related to
-specific workloads that have nothing to do with the SV Specification**
+specific workloads that have nothing to do with the SV Specification*
 
 **Additional Instructions for specific purposes (not SVP64)**