From: Claire Xenia Wolf Date: Wed, 9 Jun 2021 10:33:41 +0000 (+0200) Subject: More deadname stuff X-Git-Tag: yosys-0.10~145^2~4 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a734face3a200a6704342e61466ca85fc0c732b0;p=yosys.git More deadname stuff --- diff --git a/manual/APPNOTE_010_Verilog_to_BLIF.tex b/manual/APPNOTE_010_Verilog_to_BLIF.tex index 0d0d3e5cd..16254d593 100644 --- a/manual/APPNOTE_010_Verilog_to_BLIF.tex +++ b/manual/APPNOTE_010_Verilog_to_BLIF.tex @@ -52,7 +52,7 @@ \begin{document} \title{Yosys Application Note 010: \\ Converting Verilog to BLIF} -\author{Clifford Wolf \\ November 2013} +\author{Claire Xenia Wolf \\ November 2013} \maketitle \begin{abstract} @@ -437,12 +437,12 @@ design to fit a certain need without actually touching the RTL code. \begin{thebibliography}{9} \bibitem{yosys} -Clifford Wolf. The Yosys Open SYnthesis Suite. \\ +Claire Xenia Wolf. The Yosys Open SYnthesis Suite. \\ \url{https://yosyshq.net/yosys/} \bibitem{bigsim} yosys-bigsim, a collection of real-world Verilog designs for regression testing purposes. \\ -\url{https://github.com/cliffordwolf/yosys-bigsim} +\url{https://github.com/YosysHQ/yosys-bigsim} \bibitem{navre} Sebastien Bourdeauducq. Navr\'e AVR clone (8-bit RISC). \\ diff --git a/manual/APPNOTE_011_Design_Investigation.tex b/manual/APPNOTE_011_Design_Investigation.tex index dc2284301..881212fe9 100644 --- a/manual/APPNOTE_011_Design_Investigation.tex +++ b/manual/APPNOTE_011_Design_Investigation.tex @@ -54,7 +54,7 @@ \begin{document} \title{Yosys Application Note 011: \\ Interactive Design Investigation} -\author{Clifford Wolf \\ Original Version December 2013} +\author{Claire Xenia Wolf \\ Original Version December 2013} \maketitle \begin{abstract} @@ -1041,7 +1041,7 @@ framework for new algorithms alike. \begin{thebibliography}{9} \bibitem{yosys} -Clifford Wolf. The Yosys Open SYnthesis Suite. +Claire Xenia Wolf. The Yosys Open SYnthesis Suite. \url{https://yosyshq.net/yosys/} \bibitem{graphviz} diff --git a/manual/APPNOTE_012_Verilog_to_BTOR.tex b/manual/APPNOTE_012_Verilog_to_BTOR.tex index a96e26503..aabdc63c4 100644 --- a/manual/APPNOTE_012_Verilog_to_BTOR.tex +++ b/manual/APPNOTE_012_Verilog_to_BTOR.tex @@ -52,7 +52,7 @@ \begin{document} \title{Yosys Application Note 012: \\ Converting Verilog to BTOR} -\author{Ahmed Irfan and Clifford Wolf \\ April 2015} +\author{Ahmed Irfan and Claire Xenia Wolf \\ April 2015} \maketitle \begin{abstract} @@ -410,7 +410,7 @@ verification benchmarks with or without memories from Verilog designs. \begin{thebibliography}{9} \bibitem{yosys} -Clifford Wolf. The Yosys Open SYnthesis Suite. \\ +Claire Xenia Wolf. The Yosys Open SYnthesis Suite. \\ \url{https://yosyshq.net/yosys/} \bibitem{boolector} diff --git a/manual/CHAPTER_Auxlibs.tex b/manual/CHAPTER_Auxlibs.tex index 440ea1375..b3041078f 100644 --- a/manual/CHAPTER_Auxlibs.tex +++ b/manual/CHAPTER_Auxlibs.tex @@ -22,7 +22,7 @@ ConstEval} class provided in {\tt kernel/consteval.h}. \label{sec:SubCircuit} The files in {\tt libs/subcircuit} provide a library for solving the subcircuit -isomorphism problem. It is written by Clifford Wolf and based on the Ullmann +isomorphism problem. It is written by C. Wolf and based on the Ullmann Subgraph Isomorphism Algorithm \cite{UllmannSubgraphIsomorphism}. It is used by the {\tt extract} pass (see {\tt help extract} or Sec.~\ref{cmd:extract}). @@ -30,6 +30,6 @@ the {\tt extract} pass (see {\tt help extract} or Sec.~\ref{cmd:extract}). The files in {\tt libs/ezsat} provide a library for simplifying generating CNF formulas for SAT solvers. It also contains bindings of MiniSAT. The ezSAT -library is written by Clifford Wolf. It is used by the {\tt sat} pass (see +library is written by C. Wolf. It is used by the {\tt sat} pass (see {\tt help sat} or Sec.~\ref{cmd:sat}). diff --git a/manual/PRESENTATION_Intro.tex b/manual/PRESENTATION_Intro.tex index 22048bc3d..1c3b79fa0 100644 --- a/manual/PRESENTATION_Intro.tex +++ b/manual/PRESENTATION_Intro.tex @@ -260,7 +260,7 @@ The following slides cover an example project. This project contains three files \end{itemize} \vfill Direct link to the files: \\ \footnotesize -\url{https://github.com/cliffordwolf/yosys/tree/master/manual/PRESENTATION_Intro} +\url{https://github.com/YosysHQ/yosys/tree/master/manual/PRESENTATION_Intro} \end{frame} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% @@ -806,7 +806,7 @@ but also formal verification, reverse engineering, ...} \begin{itemize} \item Ongoing PhD project on coarse grain synthesis \\ {\setlength{\parindent}{0.5cm}\footnotesize -Johann Glaser and Clifford Wolf. Methodology and Example-Driven Interconnect +Johann Glaser and C. Wolf. Methodology and Example-Driven Interconnect Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable Architectures. In Jan Haase, editor, \it Models, Methods, and Tools for Complex Chip Design. Lecture Notes in Electrical Engineering. Volume 265, 2014, pp @@ -925,7 +925,7 @@ control logic because it is simpler than setting up a commercial flow. \bigskip \item Direct link to the source code: \\ -\smallskip\hskip1cm\url{https://github.com/cliffordwolf/yosys} +\smallskip\hskip1cm\url{https://github.com/YosysHQ/yosys} \end{itemize} \end{frame} diff --git a/manual/literature.bib b/manual/literature.bib index 372e882ac..86652eb46 100644 --- a/manual/literature.bib +++ b/manual/literature.bib @@ -1,7 +1,7 @@ @inproceedings{intersynth, title={Example-driven interconnect synthesis for heterogeneous coarse-grain reconfigurable logic}, - author={Clifford Wolf and Johann Glaser and Florian Schupfer and Jan Haase and Christoph Grimm}, + author={C. Wolf and Johann Glaser and Florian Schupfer and Jan Haase and Christoph Grimm}, booktitle={FDL Proceeding of the 2012 Forum on Specification and Design Languages}, pages={194--201}, year={2012} @@ -9,7 +9,7 @@ @incollection{intersynthFdlBookChapter, title={Methodology and Example-Driven Interconnect Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable Architectures}, - author={Johann Glaser and Clifford Wolf}, + author={Johann Glaser and C. Wolf}, booktitle={Advances in Models, Methods, and Tools for Complex Chip Design --- Selected contributions from FDL'12}, editor={Jan Haase}, publisher={Springer}, @@ -18,14 +18,14 @@ } @unpublished{BACC, - author = {Clifford Wolf}, + author = {C. Wolf}, title = {Design and Implementation of the Yosys Open SYnthesis Suite}, note = {Bachelor Thesis, Vienna University of Technology}, year = {2013} } @unpublished{VerilogFossEval, - author = {Clifford Wolf}, + author = {C. Wolf}, title = {Evaluation of Open Source Verilog Synthesis Tools for Feature-Completeness and Extensibility}, note = {Unpublished Student Research Paper, Vienna University of Technology}, year = {2012} diff --git a/manual/manual.tex b/manual/manual.tex index dac8b1000..1914df989 100644 --- a/manual/manual.tex +++ b/manual/manual.tex @@ -51,7 +51,7 @@ % Hyperlinks \usepackage[colorlinks,hyperindex,plainpages=false,% pdftitle={Yosys Manual},% -pdfauthor={Clifford Wolf},% +pdfauthor={Claire Xenia Wolf},% %pdfkeywords={keyword},% pdfpagelabels,% pagebackref,% @@ -137,7 +137,7 @@ bookmarksopen=false% \bf\Huge Yosys Manual \bigskip -\large Clifford Wolf +\large Claire Xenia Wolf \end{center} \vfil\null diff --git a/manual/presentation.tex b/manual/presentation.tex index ea8e37bc9..7aba33c8b 100644 --- a/manual/presentation.tex +++ b/manual/presentation.tex @@ -80,7 +80,7 @@ \end{centering}} \title{Yosys Open SYnthesis Suite} -\author{Clifford Wolf} +\author{Claire Xenia Wolf} \institute{https://yosyshq.net/yosys/} \usetheme{Madrid} @@ -124,7 +124,7 @@ writing extensions to Yosys using the C++ API. \section{About me} \begin{frame}{About me} -Hi! I'm Clifford Wolf. +Hi! I'm Claire Xenia Wolf. \bigskip I like writing open source software. For example: diff --git a/manual/weblinks.bib b/manual/weblinks.bib index d5f83315d..23ddbc38b 100644 --- a/manual/weblinks.bib +++ b/manual/weblinks.bib @@ -1,20 +1,20 @@ @misc{YosysGit, - author = {Clifford Wolf}, + author = {Claire Xenia Wolf}, title = {{Yosys Open SYnthesis Suite (YOSYS)}}, - note = {\url{http://github.com/cliffordwolf/yosys}} + note = {\url{http://github.com/YosysHQ/yosys}} } @misc{YosysTestsGit, - author = {Clifford Wolf}, + author = {Claire Xenia Wolf}, title = {{Yosys Test Bench}}, - note = {\url{http://github.com/cliffordwolf/yosys-tests}} + note = {\url{http://github.com/YosysHQ/yosys-tests}} } @misc{VlogHammer, - author = {Clifford Wolf}, + author = {Claire Xenia Wolf}, title = {{VlogHammer Verilog Synthesis Regression Tests}}, - note = {\url{http://github.com/cliffordwolf/VlogHammer}} + note = {\url{http://github.com/YosysHQ/VlogHammer}} } @misc{Icarus, diff --git a/tests/simple/vloghammer.v b/tests/simple/vloghammer.v index 3bb3cf992..5fcedbff1 100644 --- a/tests/simple/vloghammer.v +++ b/tests/simple/vloghammer.v @@ -1,6 +1,6 @@ // test cases found using vloghammer -// https://github.com/cliffordwolf/VlogHammer +// https://github.com/YosysHQ/VlogHammer module test01(a, y); input [7:0] a;