From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 22 Mar 2018 04:39:49 +0000 (+0000)
Subject: cell mux naming convention (forgot to save, whoops)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a739e5f8465c5afec5ec4334809bd37d319d2680;p=pinmux.git

cell mux naming convention (forgot to save, whoops)
---

diff --git a/src/wire_def.py b/src/wire_def.py
index aca972b..dd4b384 100644
--- a/src/wire_def.py
+++ b/src/wire_def.py
@@ -1,9 +1,9 @@
 # == Intermediate wire definitions ==#
 muxwire = '''
-      Wire#(Bit#({1}))   wrmux{0} <-mkDWire(0);'''
+      Wire#(Bit#({1}))   wrcell{0}_mux <-mkDWire(0);'''
 generic_io = '''
-      GenericIOType cell{0}_out=unpack(0);
-      Wire#(Bit#(1)) cell{0}_in <-mkDWire(0);
+      GenericIOType cell{0}_mux_out=unpack(0);
+      Wire#(Bit#(1)) cell{0}_mux_in <-mkDWire(0);
 '''
 uartwires = '''
       Wire#(Bit#(1)) wruart{0}_rx <-mkDWire(0);