From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 10 Sep 2022 13:18:46 +0000 (+0100)
Subject: mention ZOLC
X-Git-Tag: opf_rfc_ls005_v1~518
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a74563c15831facf10fc10dd6f41d673684dd8aa;p=libreriscv.git

mention ZOLC
---

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 97faa10af..35dbe1de3 100644
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -87,9 +87,9 @@ to provide future expanded register file bitwidths and sizes. [^msr]
 # Hardware Implementations
 
 The fundamental principle of Simple-V is that it sits between Issue and
-Decode, pausing the Program-Counter to service a "Sub-Program-Counter"
-hardware for-loop.  In practical terms for many first-version
-implementations this is sufficient.
+Decode, pausing the Program-Counter to service a "Sub-PC"
+hardware for-loop.  This is very similar to "Zero-Overhead Loops"
+in High-end DSPs (TI MSP Series).
 
 **Considerable** effort has been expended to ensure that Simple-V is
 practical to implement on an extremely wide range of Industry-wide