From: lkcl <lkcl@web>
Date: Mon, 30 Aug 2021 14:25:08 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~274
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a752d85ffd15ff05f7ab6b3120ca9f3c8bd7dab5;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index f29a9545f..5c1eab379 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -45,6 +45,9 @@ Pages being developed and examples
 * [[sv/mv.swizzle]]
 * [[sv/mv.x]]
 * [[sv/branches]] - SVP64 Conditional Branch behaviour: All/Some Vector CRs
+* [[sv/cr_ops]] - SVP64 Condition Register ops: Guidelines
+ on Vectorisation of any v3.0B base operations which return
+ or modify a Condition Register bit or field.
 * [[sv/fcvt]] FP Conversion (due to OpenPOWER Scalar FP32)
 * [[sv/fclass]] detect class of FP numbers
 * [[sv/int_fp_mv]] Move and convert GPR <-> FPR, needed for !VSX