From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 3 Nov 2018 10:25:42 +0000 (+0000)
Subject: add remap CSR set
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a75f621671960eca363dca48980ad8816dab41be;p=riscv-isa-sim.git

add remap CSR set
---

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 5c95f8c..4e15497 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -514,6 +514,16 @@ void processor_t::set_csr(int which, reg_t val)
       }
       break;
     }
+    case CSR_UREMAP:
+    {
+      state.remap[0].regidx = get_field(val, SV_REMAP_REGIDX0);
+      state.remap[1].regidx = get_field(val, SV_REMAP_REGIDX1);
+      state.remap[2].regidx = get_field(val, SV_REMAP_REGIDX2);
+      state.remap[0].shape = get_field(val, SV_REMAP_SHAPE0);
+      state.remap[1].shape = get_field(val, SV_REMAP_SHAPE1);
+      state.remap[2].shape = get_field(val, SV_REMAP_SHAPE2);
+      break;
+    }
 #endif
     case CSR_FFLAGS:
       dirty_fp_state;
diff --git a/riscv/sv.h b/riscv/sv.h
index 89ed2e9..87c1ad3 100644
--- a/riscv/sv.h
+++ b/riscv/sv.h
@@ -84,4 +84,11 @@ typedef struct {
     int permute;
 } sv_shape_t;
 
+#define SV_REMAP_REGIDX0 (0x7f)
+#define SV_REMAP_REGIDX1 (0x7f<<8)
+#define SV_REMAP_REGIDX2 (0x7f<<16)
+#define SV_REMAP_SHAPE0 (0x3<<24)
+#define SV_REMAP_SHAPE1 (0x3<<26)
+#define SV_REMAP_SHAPE2 (0x3<<28)
+
 #endif