From: Clifford Wolf Date: Sat, 13 Feb 2016 07:20:19 +0000 (+0100) Subject: Run dffsr2dff in synth_xilinx X-Git-Tag: yosys-0.6~10 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a75f94ec4ae411d98d9882e423e0ae02eda4bd37;p=yosys.git Run dffsr2dff in synth_xilinx --- diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 6358a266b..21d1fb1ea 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -91,6 +91,7 @@ struct SynthXilinxPass : public Pass { log(" fine:\n"); log(" opt -fast -full\n"); log(" memory_map\n"); + log(" dffsr2dff\n"); log(" dff2dffe\n"); log(" opt -full\n"); log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n"); @@ -196,6 +197,7 @@ struct SynthXilinxPass : public Pass { { Pass::call(design, "opt -fast -full"); Pass::call(design, "memory_map"); + Pass::call(design, "dffsr2dff"); Pass::call(design, "dff2dffe"); Pass::call(design, "opt -full"); Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v");