From: Shriya Sharma <shriya@redsemiconductor.com>
Date: Fri, 27 Oct 2023 10:33:21 +0000 (+0100)
Subject: added english language description for lwzsux instruction
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a78dee8082831b9406f0098a917699d2a57cc212;p=openpower-isa.git

added english language description for lwzsux instruction
---

diff --git a/openpower/isa/fixedloadshift.mdwn b/openpower/isa/fixedloadshift.mdwn
index 7ace250a..903019cd 100644
--- a/openpower/isa/fixedloadshift.mdwn
+++ b/openpower/isa/fixedloadshift.mdwn
@@ -218,6 +218,19 @@ Pseudo-code:
     RT <- [0] * 32 || MEM(EA, 4)
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum of the contents of
+    register RB shifted by (SH+1), and (RA).
+
+    The word in storage addressed by EA is loaded into RT[32:63].
+    RT[0:31] are set to 0.
+
+    EA is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
+
 Special Registers Altered:
 
     None