From: David Edelsohn Date: Thu, 15 Jul 1999 12:39:30 +0000 (+0000) Subject: rs6000.md (insv, extzv): Remove SImode dependence in named patterns. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a78e33fc4b62903af1b875ba51734a11a31bdffb;p=gcc.git rs6000.md (insv, extzv): Remove SImode dependence in named patterns. * rs6000.md (insv, extzv): Remove SImode dependence in named patterns. Explicitly generate DImode RTL if PowerPC64 and operand is DImode. (insvdi): Reverse start and size in instruction template. From-SVN: r28114 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4f72cdbcc18..71e7ff1c8c4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +Thu Jul 15 15:15:43 1999 David Edelsohn + + * rs6000.md (insv, extzv): Remove SImode dependence in named + patterns. Explicitly generate DImode RTL if PowerPC64 and + operand is DImode. + (insvdi): Reverse start and size in instruction template. + 1999-07-12 Joseph S. Myers * invoke.texi: Typo fixes. diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 7a97dd1f78f..085db80462d 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -2594,10 +2594,10 @@ ;; Rotate and shift insns, in all their variants. These support shifts, ;; field inserts and extracts, and various combinations thereof. (define_expand "insv" - [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") - (match_operand:SI 1 "const_int_operand" "i") - (match_operand:SI 2 "const_int_operand" "i")) - (match_operand:SI 3 "gpc_reg_operand" "r"))] + [(set (zero_extract (match_operand 0 "gpc_reg_operand" "+r") + (match_operand:SI 1 "const_int_operand" "i") + (match_operand:SI 2 "const_int_operand" "i")) + (match_operand 3 "gpc_reg_operand" "r"))] "" " { @@ -2607,9 +2607,15 @@ if (GET_CODE (operands[0]) == SUBREG && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) FAIL; + + if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode) + emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3])); + else + emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3])); + DONE; }") -(define_insn "" +(define_insn "insvsi" [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") (match_operand:SI 1 "const_int_operand" "i") (match_operand:SI 2 "const_int_operand" "i")) @@ -2625,7 +2631,7 @@ return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; }") -(define_insn "" +(define_insn "*insvsi_internal1" [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") (match_operand:SI 1 "const_int_operand" "i") (match_operand:SI 2 "const_int_operand" "i")) @@ -2643,7 +2649,7 @@ return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; }") -(define_insn "" +(define_insn "*insvsi_internal2" [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") (match_operand:SI 1 "const_int_operand" "i") (match_operand:SI 2 "const_int_operand" "i")) @@ -2661,7 +2667,7 @@ return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; }") -(define_insn "" +(define_insn "*insvsi_internal3" [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") (match_operand:SI 1 "const_int_operand" "i") (match_operand:SI 2 "const_int_operand" "i")) @@ -2679,7 +2685,7 @@ return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; }") -(define_insn "" +(define_insn "*insvsi_internal4" [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") (match_operand:SI 1 "const_int_operand" "i") (match_operand:SI 2 "const_int_operand" "i")) @@ -2700,10 +2706,10 @@ return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\"; }") -(define_insn "" +(define_insn "insvdi" [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") - (match_operand:DI 1 "const_int_operand" "i") - (match_operand:DI 2 "const_int_operand" "i")) + (match_operand:SI 1 "const_int_operand" "i") + (match_operand:SI 2 "const_int_operand" "i")) (match_operand:DI 3 "gpc_reg_operand" "r"))] "TARGET_POWERPC64" "* @@ -2711,15 +2717,15 @@ int start = INTVAL (operands[2]) & 63; int size = INTVAL (operands[1]) & 63; - operands[2] = GEN_INT (64 - start - size); - return \"rldimi %0,%3,%H2,%H1\"; + operands[1] = GEN_INT (64 - start - size); + return \"rldimi %0,%3,%H1,%H2\"; }") (define_expand "extzv" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") - (match_operand:SI 2 "const_int_operand" "i") - (match_operand:SI 3 "const_int_operand" "i")))] + [(set (match_operand 0 "gpc_reg_operand" "=r") + (zero_extract (match_operand 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "const_int_operand" "i") + (match_operand:SI 3 "const_int_operand" "i")))] "" " { @@ -2729,9 +2735,15 @@ if (GET_CODE (operands[0]) == SUBREG && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) FAIL; + + if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode) + emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3])); + else + emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3])); + DONE; }") -(define_insn "" +(define_insn "extzvsi" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i") @@ -2749,7 +2761,7 @@ return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\"; }") -(define_insn "" +(define_insn "*extzvsi_internal1" [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i") @@ -2786,7 +2798,7 @@ }" [(set_attr "type" "compare")]) -(define_insn "" +(define_insn "*extzvsi_internal2" [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i") @@ -2814,11 +2826,11 @@ }" [(set_attr "type" "delayed_compare")]) -(define_insn "" +(define_insn "extzvdi" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") - (match_operand:DI 2 "const_int_operand" "i") - (match_operand:DI 3 "const_int_operand" "i")))] + (match_operand:SI 2 "const_int_operand" "i") + (match_operand:SI 3 "const_int_operand" "i")))] "TARGET_POWERPC64" "* { @@ -2833,11 +2845,11 @@ return \"rldicl %0,%1,%3,%2\"; }") -(define_insn "" +(define_insn "*extzvdi_internal1" [(set (match_operand:CC 0 "gpc_reg_operand" "=x") (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") - (match_operand:DI 2 "const_int_operand" "i") - (match_operand:DI 3 "const_int_operand" "i")) + (match_operand:SI 2 "const_int_operand" "i") + (match_operand:SI 3 "const_int_operand" "i")) (const_int 0))) (clobber (match_scratch:DI 4 "=r"))] "TARGET_POWERPC64" @@ -2854,11 +2866,11 @@ return \"rldicl. %4,%1,%3,%2\"; }") -(define_insn "" +(define_insn "*extzvdi_internal2" [(set (match_operand:CC 4 "gpc_reg_operand" "=x") (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") - (match_operand:DI 2 "const_int_operand" "i") - (match_operand:DI 3 "const_int_operand" "i")) + (match_operand:SI 2 "const_int_operand" "i") + (match_operand:SI 3 "const_int_operand" "i")) (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "=r") (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]