From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 19 Dec 2014 18:02:31 +0000 (+0100)
Subject: prepare identify test with SATACON
X-Git-Tag: 24jan2021_ls180~2572^2~92
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a79696641a6cd6027c681fa453fb81c7f2a3e50c;p=litex.git

prepare identify test with SATACON
---

diff --git a/targets/test.py b/targets/test.py
index 9f92c81c..8115d66a 100644
--- a/targets/test.py
+++ b/targets/test.py
@@ -10,7 +10,7 @@ from miscope.uart2wishbone import UART2Wishbone
 from misoclib import identifier
 from lib.sata.common import *
 from lib.sata.phy import SATAPHY
-from lib.sata.link.cont import SATACONTInserter, SATACONTRemover
+from lib.sata import SATACON
 
 from migen.genlib.cdc import *
 
@@ -149,37 +149,28 @@ class ClockLeds(Module):
 				sata_tx_cnt.eq(sata_tx_cnt-1)
 			)
 
-class VeryBasicPHYStim(Module, AutoCSR):
-	def __init__(self, phy):
-		self._enable = CSRStorage()
-		self._tx_primitive = CSRStorage(32)
-		self._rx_primitive = CSRStatus(32)
+class IdentifyRequester(Module, AutoCSR):
+	def __init__(self, sata_con):
+		self._req = CSRStorage()
+		req = self._req.storage
 
-		self.cont_inserter = SATACONTInserter(phy_description(32))
-		self.cont_remover = SATACONTRemover(phy_description(32))
 		self.comb += [
-			self.cont_inserter.source.connect(phy.sink),
-			phy.source.connect(self.cont_remover.sink),
-			self.cont_remover.source.ack.eq(1)
-		]
-		self.sync += [
-			self.cont_inserter.sink.stb.eq(1),
-			self.cont_inserter.sink.charisk.eq(0b0001),
-			If(self._enable.storage,
-				self.cont_inserter.sink.data.eq(self._tx_primitive.storage),
-				If(self.cont_remover.source.stb & (self.cont_remover.source.charisk == 0b0001),
-					self._rx_primitive.status.eq(self.cont_remover.source.data)
-				)
-			).Else(
-				self.cont_inserter.sink.data.eq(primitives["SYNC"]),
-			)
+			sata_con.sink.stb.eq(req),
+			sata_con.sink.sop.eq(1),
+			sata_con.sink.eop.eq(1),
+			sata_con.sink.identify.eq(1),
+			sata_con.sink.sector.eq(0),
+			sata_con.sink.count.eq(1),
+			sata_con.sink.data.eq(0),
+
+			sata_con.sink.ack.eq(1),
 		]
 
 class TestDesign(UART2WB, AutoCSR):
 	default_platform = "kc705"
 	csr_map = {
-		"mila":				10,
-		"stim":             11
+		"mila":					10,
+		"identify_requester":	11
 	}
 	csr_map.update(UART2WB.csr_map)
 
@@ -189,7 +180,9 @@ class TestDesign(UART2WB, AutoCSR):
 		self.crg = _CRG(platform)
 
 		self.sata_phy = SATAPHY(platform.request("sata_host"), clk_freq, host=True, speed="SATA1")
-		self.stim = VeryBasicPHYStim(self.sata_phy)
+		self.sata_con = SATACON(self.sata_phy, sector_size=512, max_count=8)
+
+		self.identify_requester = IdentifyRequester(self.sata_con)
 
 		self.clock_leds = ClockLeds(platform)
 
@@ -214,9 +207,22 @@ class TestDesign(UART2WB, AutoCSR):
 				self.sata_phy.sink.data,
 				self.sata_phy.sink.charisk,
 
-				self.stim.cont_remover.source.stb,
-				self.stim.cont_remover.source.data,
-				self.stim.cont_remover.source.charisk
+				self.sata_con.sink.stb,
+				self.sata_con.sink.sop,
+				self.sata_con.sink.eop,
+				self.sata_con.sink.ack,
+				self.sata_con.sink.identify,
+
+				self.sata_con.source.stb,
+				self.sata_con.source.sop,
+				self.sata_con.source.eop,
+				self.sata_con.source.ack,
+				self.sata_con.source.write,
+				self.sata_con.source.read,
+				self.sata_con.source.identify,
+				self.sata_con.source.success,
+				self.sata_con.source.failed,
+				self.sata_con.source.data
 			)
 
 			self.comb += platform.request("user_led", 2).eq(crg.ready)
diff --git a/test/test_identify.py b/test/test_identify.py
new file mode 100644
index 00000000..513bded4
--- /dev/null
+++ b/test/test_identify.py
@@ -0,0 +1,23 @@
+from config import *
+from miscope.host.drivers import MiLaDriver
+
+mila = MiLaDriver(wb.regs, "mila", use_rle=False)
+wb.open()
+###
+trigger0 = mila.sata_con_sink_stb_o*1
+mask0 = mila.sata_con_sink_stb_m
+
+mila.prog_term(port=0, trigger=trigger0, mask=mask0)
+mila.prog_sum("term")
+
+# Trigger / wait / receive
+mila.trigger(offset=32, length=1024)
+regs.identify_requester_req.write(1)
+time.sleep(0.1)
+regs.identify_requester_req.write(0)
+mila.wait_done()
+mila.read()
+mila.export("dump.vcd")
+mila.export("dump.csv")
+###
+wb.close()
diff --git a/test/test_stim.py b/test/test_stim.py
deleted file mode 100644
index f3ba8726..00000000
--- a/test/test_stim.py
+++ /dev/null
@@ -1,42 +0,0 @@
-from config import *
-import time
-
-primitives = {
-	"ALIGN"	:	0x7B4A4ABC,
-	"CONT"	: 	0X9999AA7C,
-	"SYNC"	:	0xB5B5957C,
-	"R_RDY"	:	0x4A4A957C,
-	"R_OK"	:	0x3535B57C,
-	"R_ERR"	:	0x5656B57C,
-	"R_IP"	:	0X5555B57C,
-	"X_RDY"	:	0x5757B57C,
-	"CONT"	:	0x9999AA7C,
-	"WTRM"	:	0x5858B57C,
-	"SOF"	:	0x3737B57C,
-	"EOF"	:	0xD5D5B57C,
-	"HOLD"	:	0xD5D5AA7C,
-	"HOLDA"	: 	0X9595AA7C
-}
-
-def decode_primitive(dword):
-	for k, v in primitives.items():
-		if dword == v:
-			return k
-	return ""
-
-wb.open()
-regs = wb.regs
-###
-regs.stim_enable.write(1)
-regs.stim_tx_primitive.write(primitives["SYNC"])
-for i in range(16):
-	rx = regs.stim_rx_primitive.read()
-	print("rx: %08x %s" %(rx, decode_primitive(rx)))
-	time.sleep(0.1)
-#regs.stim_tx_primitive.write(primitives["X_RDY"])
-for i in range(16):
-	rx = regs.stim_rx_primitive.read()
-	print("rx: %08x %s" %(rx, decode_primitive(rx)))
-	time.sleep(0.1)
-###
-wb.close()