From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 5 Jan 2013 10:44:47 +0000 (+0100)
Subject: Copy attributes from state signal to fsm cell
X-Git-Tag: yosys-0.2.0~802
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a7988c01af4bab7390c60fdde04b92ed816aa306;p=yosys.git

Copy attributes from state signal to fsm cell
---

diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
index bdcb1d45a..c89078cd3 100644
--- a/passes/fsm/fsm_extract.cc
+++ b/passes/fsm/fsm_extract.cc
@@ -283,6 +283,7 @@ static void extract_fsm(RTLIL::Wire *wire)
 	fsm_cell->connections["\\CTRL_IN"] = ctrl_in;
 	fsm_cell->connections["\\CTRL_OUT"] = ctrl_out;
 	fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name);
+    fsm_cell->attributes = wire->attributes;
 	fsm_data.copy_to_cell(fsm_cell);
 	module->cells[fsm_cell->name] = fsm_cell;