From: Luke Kenneth Casson Leighton Date: Sat, 20 Jun 2020 12:25:57 +0000 (+0100) Subject: add assertion checking bus write against memory write port granularity X-Git-Tag: 24jan2021_ls180~5 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a79def076ad4979cefc2047b8001a8a12df0ea64;p=nmigen-soc.git add assertion checking bus write against memory write port granularity --- diff --git a/nmigen_soc/wishbone/sram.py b/nmigen_soc/wishbone/sram.py index 630b53c..c518ff9 100644 --- a/nmigen_soc/wishbone/sram.py +++ b/nmigen_soc/wishbone/sram.py @@ -86,7 +86,11 @@ class SRAM(Elaboratable): wrport.addr.eq(self.bus.adr[:len(rdport.addr)]), wrport.data.eq(self.bus.dat_w) ] - for i in range(4): + n_wrport = wrport.en.shape()[0] + n_bussel = self.bus.sel.shape()[0] + assert n_wrport == n_bussel, "bus enable count %d " \ + "must match memory wen count %d" % (n_wrport, n_bussel) + for i in range(n_wrport): m.d.comb += wrport.en[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i])