From: AdithyaGopan <AdithyaGopan@web>
Date: Wed, 18 Aug 2021 16:21:50 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~392
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a79ff5e3838ad106964ebeb3e022bfacfe08d122;p=libreriscv.git

---

diff --git a/oa/adithya.mdwn b/oa/adithya.mdwn
new file mode 100644
index 000000000..7f3522038
--- /dev/null
+++ b/oa/adithya.mdwn
@@ -0,0 +1,3 @@
+* Interests:Digital System Design,PCB layout, Programming, Machine Learning, IoT
+* Programming Languages: Verilog, C, C++, Java, Python3, Julia
+* Availability: ~10hrs per week