From: Richard Kenner <kenner@gcc.gnu.org>
Date: Sun, 19 Apr 1992 10:08:02 +0000 (-0400)
Subject: *** empty log message ***
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a7a975e119735ca9f01ddf3fa1189ea599b888b0;p=gcc.git

*** empty log message ***

From-SVN: r791
---

diff --git a/gcc/config/romp/romp.h b/gcc/config/romp/romp.h
index bfb5a133e37..0c06624092b 100644
--- a/gcc/config/romp/romp.h
+++ b/gcc/config/romp/romp.h
@@ -1234,20 +1234,22 @@ struct rt_cargs {int gregs, fregs; };
 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
   case CONST_INT:						\
     if ((OUTER_CODE) == IOR && exact_log2 (INTVAL (RTX)) >= 0	\
-	|| (OUTER_CODE) == AND && exact_log2 (~INTVAL (RTX)) >= 0	\
-	|| (((OUTER_CODE) == PLUS || (OUTER_CODE) == MINUS)		\
+	|| (OUTER_CODE) == AND && exact_log2 (~INTVAL (RTX)) >= 0 \
+	|| (((OUTER_CODE) == PLUS || (OUTER_CODE) == MINUS)	\
 	    && (unsigned int) (INTVAL (RTX) + 15) < 31)		\
 	|| ((OUTER_CODE) == SET && (unsigned int) INTVAL (RTX) < 16))\
       return 0;							\
-    return ((unsigned)(INTVAL(RTX) + 0x8000) < 0x10000 || (INTVAL (RTX) & 0xffff0000) == 0) ? 0 : COSTS_N_INSNS (2);\
+    return ((unsigned int) (INTVAL(RTX) + 0x8000) < 0x10000		\
+	    || (INTVAL (RTX) & 0xffff0000) == 0) ? 0 : COSTS_N_INSNS (2);\
   case CONST:							\
   case LABEL_REF:						\
   case SYMBOL_REF:						\
     if (current_function_operand (RTX, Pmode)) return 0;	\
-    return COSTS_N_INSNS (2);
+    return COSTS_N_INSNS (2);					\
   case CONST_DOUBLE:						\
     if ((RTX) == CONST0_RTX (GET_MODE (RTX))) return 2;		\
-    return (GET_MODE_CLASS (GET_MODE (RTX)) == MODE_FLOAT) ? COSTS_N_INSNS (5) : COSTS_N_INSNS (4);
+    return ((GET_MODE_CLASS (GET_MODE (RTX)) == MODE_FLOAT)	\
+	    ? COSTS_N_INSNS (5) : COSTS_N_INSNS (4));
 
 /* Provide the costs of a rtl expression.  This is in the body of a
    switch on CODE. 
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 68cc0582954..39de456de2e 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -1081,7 +1081,13 @@
   int start = INTVAL (operands[3]) & 31;
   int size = INTVAL (operands[2]) & 31;
 
-  if ((start < 16 && start + size <= 16) || start >= 16)
+  /* If the bitfield being tested fits in the upper or lower half of a
+     word, it is possible to use andiu. or andil. to test it.  This is
+     useful because the condition register set-use delay is smaller for
+     andi[ul]. than for rlinm.  This doesn't work when the starting bit
+     position is 0 because the LT and GT bits may be set wrong.  */
+
+  if ((start > 0 && start + size <= 16) || start >= 16)
     {
       operands[3] = gen_rtx (CONST_INT, VOIDmode,
 			     ((1 << (16 - (start & 15)))
@@ -1114,15 +1120,10 @@
   int start = INTVAL (operands[3]) & 31;
   int size = INTVAL (operands[2]) & 31;
 
-  if ((start < 16 && start + size <= 16) || start >= 16)
+  if (start >= 16 && start + size == 32)
     {
-      operands[3] = gen_rtx (CONST_INT, VOIDmode,
-			     ((1 << (16 - (start & 15)))
-			      - (1 << (16 - (start & 15) - size))));
-      if (start < 16)
-	return \"andiu. %0,%1,%3\";
-      else
-	return \"andil. %0,%1,%3\";
+      operands[3] = gen_rtx (CONST_INT, VOIDmode, (1 << (32 - start)) - 1);
+      return \"andil. %0,%1,%3\";
     }
   
   if (start + size >= 32)