From: Claire Wolf <claire@symbioticeda.com>
Date: Sun, 8 Mar 2020 15:12:12 +0000 (+0100)
Subject: Fix partsel expr bit width handling and add test case
X-Git-Tag: working-ls180~768^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a7cc4673c3f75f414a82c81a507da5042bba361f;p=yosys.git

Fix partsel expr bit width handling and add test case

Signed-off-by: Claire Wolf <claire@symbioticeda.com>
---

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index be8b39e9f..91982e2a3 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -593,13 +593,15 @@ non_opt_range:
 	} |
 	'[' expr TOK_POS_INDEXED expr ']' {
 		$$ = new AstNode(AST_RANGE);
-		$$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, $2->clone(), $4), AstNode::mkconst_int(1, true)));
-		$$->children.push_back(new AstNode(AST_ADD, $2, AstNode::mkconst_int(0, true)));
+		AstNode *expr = new AstNode(AST_CONCAT, $2);
+		$$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, expr->clone(), $4), AstNode::mkconst_int(1, true)));
+		$$->children.push_back(new AstNode(AST_ADD, expr, AstNode::mkconst_int(0, true)));
 	} |
 	'[' expr TOK_NEG_INDEXED expr ']' {
 		$$ = new AstNode(AST_RANGE);
-		$$->children.push_back(new AstNode(AST_ADD, $2, AstNode::mkconst_int(0, true)));
-		$$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, $2->clone(), AstNode::mkconst_int(1, true)), $4));
+		AstNode *expr = new AstNode(AST_CONCAT, $2);
+		$$->children.push_back(new AstNode(AST_ADD, expr, AstNode::mkconst_int(0, true)));
+		$$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, expr->clone(), AstNode::mkconst_int(1, true)), $4));
 	} |
 	'[' expr ']' {
 		$$ = new AstNode(AST_RANGE);
diff --git a/tests/simple/partsel.v b/tests/simple/partsel.v
index 7461358ad..83493fcb0 100644
--- a/tests/simple/partsel.v
+++ b/tests/simple/partsel.v
@@ -60,3 +60,7 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+module partsel_test003(input [2:0] a, b, input [31:0] din, output [3:0] dout);
+assign dout = din[a*b +: 2];
+endmodule