From: lkcl <lkcl@web>
Date: Sat, 23 Oct 2021 17:49:44 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~3550
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a7cd23e8360395288e85b5949cd83bd347883d73;p=libreriscv.git

---

diff --git a/3d_gpu/architecture/dynamic_simd/slice.mdwn b/3d_gpu/architecture/dynamic_simd/slice.mdwn
index 1c1f40e0e..f17648ca0 100644
--- a/3d_gpu/architecture/dynamic_simd/slice.mdwn
+++ b/3d_gpu/architecture/dynamic_simd/slice.mdwn
@@ -170,6 +170,17 @@ does not:
 SimdSignal of only 8 bits in length or so, but having a **different**
 style of PartitionPoints, with no padding this time)
 
+take signal a, of 16 bits, each bit being numbered in hexadecimal:
+
+            |        |        |
+    AfAeAdAc AbAaA9A8 A7A6A5A4 A3A2A1A0
+
+and take a slice a[0:2] to create 3-bit values, where padding is
+specified by "x", at each elwid:
+
+    elwid        |        |        |
+    0b00 AfAeAdAc AbAaA9A8 A7A6A5A4 A3A2A1A0
+
 Illustrating the case where a Sliced (fixed element width) SimdSignal
 is added to one which has variable-length elements that take up the
 entirety of the partition (overall fixed width):