From: Zack Rusin Date: Mon, 26 Jan 2009 19:37:21 +0000 (-0500) Subject: gallium: standardize naming of masks X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a7e72231e3c76a9410d192441da309002ea6422d;p=mesa.git gallium: standardize naming of masks --- diff --git a/src/gallium/drivers/cell/ppu/cell_gen_fragment.c b/src/gallium/drivers/cell/ppu/cell_gen_fragment.c index 0ea8f017ef9..9bdc71b676e 100644 --- a/src/gallium/drivers/cell/ppu/cell_gen_fragment.c +++ b/src/gallium/drivers/cell/ppu/cell_gen_fragment.c @@ -1187,7 +1187,7 @@ gen_stencil_test(struct spe_function *f, */ switch (state->func) { case PIPE_FUNC_EQUAL: - if (state->value_mask == stencil_max_value) { + if (state->valuemask == stencil_max_value) { /* stencil_pass = fragment_mask & (s == reference) */ spe_compare_equal_uint(f, stencil_pass_reg, fbS_reg, state->ref_value); spe_and(f, stencil_pass_reg, fragment_mask_reg, stencil_pass_reg); @@ -1195,16 +1195,16 @@ gen_stencil_test(struct spe_function *f, else { /* stencil_pass = fragment_mask & ((s&mask) == (reference&mask)) */ uint tmp_masked_stencil = spe_allocate_available_register(f); - spe_and_uint(f, tmp_masked_stencil, fbS_reg, state->value_mask); + spe_and_uint(f, tmp_masked_stencil, fbS_reg, state->valuemask); spe_compare_equal_uint(f, stencil_pass_reg, tmp_masked_stencil, - state->value_mask & state->ref_value); + state->valuemask & state->ref_value); spe_and(f, stencil_pass_reg, fragment_mask_reg, stencil_pass_reg); spe_release_register(f, tmp_masked_stencil); } break; case PIPE_FUNC_NOTEQUAL: - if (state->value_mask == stencil_max_value) { + if (state->valuemask == stencil_max_value) { /* stencil_pass = fragment_mask & ~(s == reference) */ spe_compare_equal_uint(f, stencil_pass_reg, fbS_reg, state->ref_value); spe_andc(f, stencil_pass_reg, fragment_mask_reg, stencil_pass_reg); @@ -1212,16 +1212,16 @@ gen_stencil_test(struct spe_function *f, else { /* stencil_pass = fragment_mask & ~((s&mask) == (reference&mask)) */ int tmp_masked_stencil = spe_allocate_available_register(f); - spe_and_uint(f, tmp_masked_stencil, fbS_reg, state->value_mask); + spe_and_uint(f, tmp_masked_stencil, fbS_reg, state->valuemask); spe_compare_equal_uint(f, stencil_pass_reg, tmp_masked_stencil, - state->value_mask & state->ref_value); + state->valuemask & state->ref_value); spe_andc(f, stencil_pass_reg, fragment_mask_reg, stencil_pass_reg); spe_release_register(f, tmp_masked_stencil); } break; case PIPE_FUNC_LESS: - if (state->value_mask == stencil_max_value) { + if (state->valuemask == stencil_max_value) { /* stencil_pass = fragment_mask & (reference < s) */ spe_compare_greater_uint(f, stencil_pass_reg, fbS_reg, state->ref_value); spe_and(f, stencil_pass_reg, fragment_mask_reg, stencil_pass_reg); @@ -1229,16 +1229,16 @@ gen_stencil_test(struct spe_function *f, else { /* stencil_pass = fragment_mask & ((reference&mask) < (s & mask)) */ int tmp_masked_stencil = spe_allocate_available_register(f); - spe_and_uint(f, tmp_masked_stencil, fbS_reg, state->value_mask); + spe_and_uint(f, tmp_masked_stencil, fbS_reg, state->valuemask); spe_compare_greater_uint(f, stencil_pass_reg, tmp_masked_stencil, - state->value_mask & state->ref_value); + state->valuemask & state->ref_value); spe_and(f, stencil_pass_reg, fragment_mask_reg, stencil_pass_reg); spe_release_register(f, tmp_masked_stencil); } break; case PIPE_FUNC_GREATER: - if (state->value_mask == stencil_max_value) { + if (state->valuemask == stencil_max_value) { /* stencil_pass = fragment_mask & (reference > s) */ /* There's no convenient Compare Less Than Immediate instruction, so * we'll have to do this one the harder way, by loading a register and @@ -1255,8 +1255,8 @@ gen_stencil_test(struct spe_function *f, /* stencil_pass = fragment_mask & ((reference&mask) > (s&mask)) */ int tmp_reg = spe_allocate_available_register(f); int tmp_masked_stencil = spe_allocate_available_register(f); - spe_load_uint(f, tmp_reg, state->value_mask & state->ref_value); - spe_and_uint(f, tmp_masked_stencil, fbS_reg, state->value_mask); + spe_load_uint(f, tmp_reg, state->valuemask & state->ref_value); + spe_and_uint(f, tmp_masked_stencil, fbS_reg, state->valuemask); spe_clgt(f, stencil_pass_reg, tmp_reg, tmp_masked_stencil); spe_and(f, stencil_pass_reg, fragment_mask_reg, stencil_pass_reg); spe_release_register(f, tmp_reg); @@ -1265,7 +1265,7 @@ gen_stencil_test(struct spe_function *f, break; case PIPE_FUNC_GEQUAL: - if (state->value_mask == stencil_max_value) { + if (state->valuemask == stencil_max_value) { /* stencil_pass = fragment_mask & (reference >= s) * = fragment_mask & ~(s > reference) */ spe_compare_greater_uint(f, stencil_pass_reg, fbS_reg, @@ -1275,16 +1275,16 @@ gen_stencil_test(struct spe_function *f, else { /* stencil_pass = fragment_mask & ~((s&mask) > (reference&mask)) */ int tmp_masked_stencil = spe_allocate_available_register(f); - spe_and_uint(f, tmp_masked_stencil, fbS_reg, state->value_mask); + spe_and_uint(f, tmp_masked_stencil, fbS_reg, state->valuemask); spe_compare_greater_uint(f, stencil_pass_reg, tmp_masked_stencil, - state->value_mask & state->ref_value); + state->valuemask & state->ref_value); spe_andc(f, stencil_pass_reg, fragment_mask_reg, stencil_pass_reg); spe_release_register(f, tmp_masked_stencil); } break; case PIPE_FUNC_LEQUAL: - if (state->value_mask == stencil_max_value) { + if (state->valuemask == stencil_max_value) { /* stencil_pass = fragment_mask & (reference <= s) ] * = fragment_mask & ~(reference > s) */ /* As above, we have to do this by loading a register */ @@ -1298,8 +1298,8 @@ gen_stencil_test(struct spe_function *f, /* stencil_pass = fragment_mask & ~((reference&mask) > (s&mask)) */ int tmp_reg = spe_allocate_available_register(f); int tmp_masked_stencil = spe_allocate_available_register(f); - spe_load_uint(f, tmp_reg, state->ref_value & state->value_mask); - spe_and_uint(f, tmp_masked_stencil, fbS_reg, state->value_mask); + spe_load_uint(f, tmp_reg, state->ref_value & state->valuemask); + spe_and_uint(f, tmp_masked_stencil, fbS_reg, state->valuemask); spe_clgt(f, stencil_pass_reg, tmp_reg, tmp_masked_stencil); spe_andc(f, stencil_pass_reg, fragment_mask_reg, stencil_pass_reg); spe_release_register(f, tmp_reg); @@ -1600,14 +1600,14 @@ gen_stencil_depth_test(struct spe_function *f, need_to_calculate_stencil_values = FALSE; need_to_writemask_stencil_values = FALSE; } - else if (stencil->write_mask == 0x0) { + else if (stencil->writemask == 0x0) { /* All changes are writemasked out, so no need to calculate * what those changes might be, and no need to write anything back. */ need_to_calculate_stencil_values = FALSE; need_to_writemask_stencil_values = FALSE; } - else if (stencil->write_mask == 0xff) { + else if (stencil->writemask == 0xff) { /* Still trivial, but a little less so. We need to write the stencil * values, but we don't need to mask them. */ @@ -1627,7 +1627,7 @@ gen_stencil_depth_test(struct spe_function *f, */ spe_comment(f, 0, "Computing stencil writemask"); stencil_writemask_reg = spe_allocate_available_register(f); - spe_load_uint(f, stencil_writemask_reg, dsa->stencil[facing].write_mask); + spe_load_uint(f, stencil_writemask_reg, dsa->stencil[facing].writemask); } /* At least one-sided stenciling must be on. Generate code that diff --git a/src/gallium/drivers/cell/ppu/cell_state_per_fragment.c b/src/gallium/drivers/cell/ppu/cell_state_per_fragment.c index 78cb446c14a..d97c22b2efe 100644 --- a/src/gallium/drivers/cell/ppu/cell_state_per_fragment.c +++ b/src/gallium/drivers/cell/ppu/cell_state_per_fragment.c @@ -297,7 +297,7 @@ emit_stencil_test(struct pipe_depth_stencil_alpha_state *dsa, int face_stencil = spe_allocate_available_register(f); int stencil_src = stencil; const unsigned ref = (dsa->stencil[face].ref_value - & dsa->stencil[face].value_mask); + & dsa->stencil[face].valuemask); boolean complement = FALSE; int stored; int tmp = spe_allocate_available_register(f); @@ -305,9 +305,9 @@ emit_stencil_test(struct pipe_depth_stencil_alpha_state *dsa, if ((dsa->stencil[face].func != PIPE_FUNC_NEVER) && (dsa->stencil[face].func != PIPE_FUNC_ALWAYS) - && (dsa->stencil[face].value_mask != 0x0ff)) { + && (dsa->stencil[face].valuemask != 0x0ff)) { stored = spe_allocate_available_register(f); - spe_andi(f, stored, stencil, dsa->stencil[face].value_mask); + spe_andi(f, stored, stencil, dsa->stencil[face].valuemask); } else { stored = stencil; } @@ -395,7 +395,7 @@ emit_stencil_test(struct pipe_depth_stencil_alpha_state *dsa, * - For depth-pass if the stencil test is NEVER * - Any of the 3 conditions if the operation is KEEP */ - if (dsa->stencil[face].write_mask != 0) { + if (dsa->stencil[face].writemask != 0) { if ((dsa->stencil[face].func != PIPE_FUNC_ALWAYS) && (dsa->stencil[face].fail_op != PIPE_STENCIL_OP_KEEP)) { if (complement) { @@ -449,10 +449,10 @@ emit_stencil_test(struct pipe_depth_stencil_alpha_state *dsa, */ if (stencil_src == stencil) { spe_release_register(f, face_stencil); - } else if (dsa->stencil[face].write_mask != 0x0ff) { + } else if (dsa->stencil[face].writemask != 0x0ff) { int tmp = spe_allocate_available_register(f); - spe_il(f, tmp, dsa->stencil[face].write_mask); + spe_il(f, tmp, dsa->stencil[face].writemask); spe_selb(f, stencil_src, stencil, stencil_src, tmp); spe_release_register(f, tmp); @@ -580,8 +580,8 @@ cell_generate_depth_stencil_test(struct cell_depth_stencil_alpha_state *cdsa) dsa->stencil[i].zpass_op); printf("# ref value / value mask / write mask: %02x %02x %02x\n", dsa->stencil[i].ref_value, - dsa->stencil[i].value_mask, - dsa->stencil[i].write_mask); + dsa->stencil[i].valuemask, + dsa->stencil[i].writemask); } printf("\t.text\n"); diff --git a/src/gallium/drivers/i915simple/i915_state.c b/src/gallium/drivers/i915simple/i915_state.c index d2487d82778..92365f6a7a2 100644 --- a/src/gallium/drivers/i915simple/i915_state.c +++ b/src/gallium/drivers/i915simple/i915_state.c @@ -318,8 +318,8 @@ i915_create_depth_stencil_state(struct pipe_context *pipe, struct i915_depth_stencil_state *cso = CALLOC_STRUCT( i915_depth_stencil_state ); { - int testmask = depth_stencil->stencil[0].value_mask & 0xff; - int writemask = depth_stencil->stencil[0].write_mask & 0xff; + int testmask = depth_stencil->stencil[0].valuemask & 0xff; + int writemask = depth_stencil->stencil[0].writemask & 0xff; cso->stencil_modes4 |= (_3DSTATE_MODES_4_CMD | ENABLE_STENCIL_TEST_MASK | @@ -350,8 +350,8 @@ i915_create_depth_stencil_state(struct pipe_context *pipe, int dfop = i915_translate_stencil_op(depth_stencil->stencil[1].zfail_op); int dpop = i915_translate_stencil_op(depth_stencil->stencil[1].zpass_op); int ref = depth_stencil->stencil[1].ref_value & 0xff; - int tmask = depth_stencil->stencil[1].value_mask & 0xff; - int wmask = depth_stencil->stencil[1].write_mask & 0xff; + int tmask = depth_stencil->stencil[1].valuemask & 0xff; + int wmask = depth_stencil->stencil[1].writemask & 0xff; cso->bfo[0] = (_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_FUNCS | diff --git a/src/gallium/drivers/i965simple/brw_cc.c b/src/gallium/drivers/i965simple/brw_cc.c index 79d4150383a..6191e73d12d 100644 --- a/src/gallium/drivers/i965simple/brw_cc.c +++ b/src/gallium/drivers/i965simple/brw_cc.c @@ -166,8 +166,8 @@ static void upload_cc_unit( struct brw_context *brw ) cc.cc0.stencil_pass_depth_pass_op = brw_translate_stencil_op( brw->attribs.DepthStencil->stencil[0].zpass_op); cc.cc1.stencil_ref = brw->attribs.DepthStencil->stencil[0].ref_value; - cc.cc1.stencil_write_mask = brw->attribs.DepthStencil->stencil[0].write_mask; - cc.cc1.stencil_test_mask = brw->attribs.DepthStencil->stencil[0].value_mask; + cc.cc1.stencil_write_mask = brw->attribs.DepthStencil->stencil[0].writemask; + cc.cc1.stencil_test_mask = brw->attribs.DepthStencil->stencil[0].valuemask; if (brw->attribs.DepthStencil->stencil[1].enabled) { cc.cc0.bf_stencil_enable = brw->attribs.DepthStencil->stencil[1].enabled; @@ -180,14 +180,14 @@ static void upload_cc_unit( struct brw_context *brw ) cc.cc0.bf_stencil_pass_depth_pass_op = brw_translate_stencil_op( brw->attribs.DepthStencil->stencil[1].zpass_op); cc.cc1.bf_stencil_ref = brw->attribs.DepthStencil->stencil[1].ref_value; - cc.cc2.bf_stencil_write_mask = brw->attribs.DepthStencil->stencil[1].write_mask; - cc.cc2.bf_stencil_test_mask = brw->attribs.DepthStencil->stencil[1].value_mask; + cc.cc2.bf_stencil_write_mask = brw->attribs.DepthStencil->stencil[1].writemask; + cc.cc2.bf_stencil_test_mask = brw->attribs.DepthStencil->stencil[1].valuemask; } /* Not really sure about this: */ - if (brw->attribs.DepthStencil->stencil[0].write_mask || - brw->attribs.DepthStencil->stencil[1].write_mask) + if (brw->attribs.DepthStencil->stencil[0].writemask || + brw->attribs.DepthStencil->stencil[1].writemask) cc.cc0.stencil_write_enable = 1; } diff --git a/src/gallium/drivers/i965simple/brw_wm.c b/src/gallium/drivers/i965simple/brw_wm.c index 8de565b96cd..10161f2d2f6 100644 --- a/src/gallium/drivers/i965simple/brw_wm.c +++ b/src/gallium/drivers/i965simple/brw_wm.c @@ -111,8 +111,8 @@ static void brw_wm_populate_key( struct brw_context *brw, if (brw->attribs.DepthStencil->stencil[0].enabled) { lookup |= IZ_STENCIL_TEST_ENABLE_BIT; - if (brw->attribs.DepthStencil->stencil[0].write_mask || - brw->attribs.DepthStencil->stencil[1].write_mask) + if (brw->attribs.DepthStencil->stencil[0].writemask || + brw->attribs.DepthStencil->stencil[1].writemask) lookup |= IZ_STENCIL_WRITE_ENABLE_BIT; } diff --git a/src/gallium/drivers/nv10/nv10_state.c b/src/gallium/drivers/nv10/nv10_state.c index d2375aa2f64..e401b3590e1 100644 --- a/src/gallium/drivers/nv10/nv10_state.c +++ b/src/gallium/drivers/nv10/nv10_state.c @@ -342,10 +342,10 @@ nv10_depth_stencil_alpha_state_create(struct pipe_context *pipe, hw->depth.test_enable = cso->depth.enabled ? 1 : 0; hw->stencil.enable = cso->stencil[0].enabled ? 1 : 0; - hw->stencil.wmask = cso->stencil[0].write_mask; + hw->stencil.wmask = cso->stencil[0].writemask; hw->stencil.func = nvgl_comparison_op(cso->stencil[0].func); hw->stencil.ref = cso->stencil[0].ref_value; - hw->stencil.vmask = cso->stencil[0].value_mask; + hw->stencil.vmask = cso->stencil[0].valuemask; hw->stencil.fail = nvgl_stencil_op(cso->stencil[0].fail_op); hw->stencil.zfail = nvgl_stencil_op(cso->stencil[0].zfail_op); hw->stencil.zpass = nvgl_stencil_op(cso->stencil[0].zpass_op); diff --git a/src/gallium/drivers/nv20/nv20_state.c b/src/gallium/drivers/nv20/nv20_state.c index 21bde5b81f9..8eb2bee93d3 100644 --- a/src/gallium/drivers/nv20/nv20_state.c +++ b/src/gallium/drivers/nv20/nv20_state.c @@ -335,10 +335,10 @@ nv20_depth_stencil_alpha_state_create(struct pipe_context *pipe, hw->depth.test_enable = cso->depth.enabled ? 1 : 0; hw->stencil.enable = cso->stencil[0].enabled ? 1 : 0; - hw->stencil.wmask = cso->stencil[0].write_mask; + hw->stencil.wmask = cso->stencil[0].writemask; hw->stencil.func = nvgl_comparison_op(cso->stencil[0].func); hw->stencil.ref = cso->stencil[0].ref_value; - hw->stencil.vmask = cso->stencil[0].value_mask; + hw->stencil.vmask = cso->stencil[0].valuemask; hw->stencil.fail = nvgl_stencil_op(cso->stencil[0].fail_op); hw->stencil.zfail = nvgl_stencil_op(cso->stencil[0].zfail_op); hw->stencil.zpass = nvgl_stencil_op(cso->stencil[0].zpass_op); diff --git a/src/gallium/drivers/nv30/nv30_state.c b/src/gallium/drivers/nv30/nv30_state.c index 47e1a625afa..2ae66e70859 100644 --- a/src/gallium/drivers/nv30/nv30_state.c +++ b/src/gallium/drivers/nv30/nv30_state.c @@ -449,10 +449,10 @@ nv30_depth_stencil_alpha_state_create(struct pipe_context *pipe, if (cso->stencil[0].enabled) { so_method(so, rankine, NV34TCL_STENCIL_FRONT_ENABLE, 8); so_data (so, cso->stencil[0].enabled ? 1 : 0); - so_data (so, cso->stencil[0].write_mask); + so_data (so, cso->stencil[0].writemask); so_data (so, nvgl_comparison_op(cso->stencil[0].func)); so_data (so, cso->stencil[0].ref_value); - so_data (so, cso->stencil[0].value_mask); + so_data (so, cso->stencil[0].valuemask); so_data (so, nvgl_stencil_op(cso->stencil[0].fail_op)); so_data (so, nvgl_stencil_op(cso->stencil[0].zfail_op)); so_data (so, nvgl_stencil_op(cso->stencil[0].zpass_op)); @@ -464,10 +464,10 @@ nv30_depth_stencil_alpha_state_create(struct pipe_context *pipe, if (cso->stencil[1].enabled) { so_method(so, rankine, NV34TCL_STENCIL_BACK_ENABLE, 8); so_data (so, cso->stencil[1].enabled ? 1 : 0); - so_data (so, cso->stencil[1].write_mask); + so_data (so, cso->stencil[1].writemask); so_data (so, nvgl_comparison_op(cso->stencil[1].func)); so_data (so, cso->stencil[1].ref_value); - so_data (so, cso->stencil[1].value_mask); + so_data (so, cso->stencil[1].valuemask); so_data (so, nvgl_stencil_op(cso->stencil[1].fail_op)); so_data (so, nvgl_stencil_op(cso->stencil[1].zfail_op)); so_data (so, nvgl_stencil_op(cso->stencil[1].zpass_op)); diff --git a/src/gallium/drivers/nv40/nv40_state.c b/src/gallium/drivers/nv40/nv40_state.c index 255c4b294d1..34d109f9af7 100644 --- a/src/gallium/drivers/nv40/nv40_state.c +++ b/src/gallium/drivers/nv40/nv40_state.c @@ -459,10 +459,10 @@ nv40_depth_stencil_alpha_state_create(struct pipe_context *pipe, if (cso->stencil[0].enabled) { so_method(so, curie, NV40TCL_STENCIL_FRONT_ENABLE, 8); so_data (so, cso->stencil[0].enabled ? 1 : 0); - so_data (so, cso->stencil[0].write_mask); + so_data (so, cso->stencil[0].writemask); so_data (so, nvgl_comparison_op(cso->stencil[0].func)); so_data (so, cso->stencil[0].ref_value); - so_data (so, cso->stencil[0].value_mask); + so_data (so, cso->stencil[0].valuemask); so_data (so, nvgl_stencil_op(cso->stencil[0].fail_op)); so_data (so, nvgl_stencil_op(cso->stencil[0].zfail_op)); so_data (so, nvgl_stencil_op(cso->stencil[0].zpass_op)); @@ -474,10 +474,10 @@ nv40_depth_stencil_alpha_state_create(struct pipe_context *pipe, if (cso->stencil[1].enabled) { so_method(so, curie, NV40TCL_STENCIL_BACK_ENABLE, 8); so_data (so, cso->stencil[1].enabled ? 1 : 0); - so_data (so, cso->stencil[1].write_mask); + so_data (so, cso->stencil[1].writemask); so_data (so, nvgl_comparison_op(cso->stencil[1].func)); so_data (so, cso->stencil[1].ref_value); - so_data (so, cso->stencil[1].value_mask); + so_data (so, cso->stencil[1].valuemask); so_data (so, nvgl_stencil_op(cso->stencil[1].fail_op)); so_data (so, nvgl_stencil_op(cso->stencil[1].zfail_op)); so_data (so, nvgl_stencil_op(cso->stencil[1].zpass_op)); diff --git a/src/gallium/drivers/nv50/nv50_state.c b/src/gallium/drivers/nv50/nv50_state.c index 38c1d938b8e..ac236db2983 100644 --- a/src/gallium/drivers/nv50/nv50_state.c +++ b/src/gallium/drivers/nv50/nv50_state.c @@ -403,8 +403,8 @@ nv50_depth_stencil_alpha_state_create(struct pipe_context *pipe, so_data (so, nvgl_comparison_op(cso->stencil[0].func)); so_method(so, tesla, NV50TCL_STENCIL_BACK_FUNC_REF, 3); so_data (so, cso->stencil[0].ref_value); - so_data (so, cso->stencil[0].write_mask); - so_data (so, cso->stencil[0].value_mask); + so_data (so, cso->stencil[0].writemask); + so_data (so, cso->stencil[0].valuemask); } else { so_method(so, tesla, NV50TCL_STENCIL_BACK_ENABLE, 1); so_data (so, 0); @@ -418,8 +418,8 @@ nv50_depth_stencil_alpha_state_create(struct pipe_context *pipe, so_data (so, nvgl_stencil_op(cso->stencil[1].zpass_op)); so_data (so, nvgl_comparison_op(cso->stencil[1].func)); so_data (so, cso->stencil[1].ref_value); - so_data (so, cso->stencil[1].write_mask); - so_data (so, cso->stencil[1].value_mask); + so_data (so, cso->stencil[1].writemask); + so_data (so, cso->stencil[1].valuemask); } else { so_method(so, tesla, NV50TCL_STENCIL_FRONT_ENABLE, 1); so_data (so, 0); diff --git a/src/gallium/drivers/softpipe/sp_quad_stencil.c b/src/gallium/drivers/softpipe/sp_quad_stencil.c index abb54877487..7495515764a 100644 --- a/src/gallium/drivers/softpipe/sp_quad_stencil.c +++ b/src/gallium/drivers/softpipe/sp_quad_stencil.c @@ -222,8 +222,8 @@ stencil_test_quad(struct quad_stage *qs, struct quad_header *quad) zFailOp = softpipe->depth_stencil->stencil[face].zfail_op; zPassOp = softpipe->depth_stencil->stencil[face].zpass_op; ref = softpipe->depth_stencil->stencil[face].ref_value; - wrtMask = softpipe->depth_stencil->stencil[face].write_mask; - valMask = softpipe->depth_stencil->stencil[face].value_mask; + wrtMask = softpipe->depth_stencil->stencil[face].writemask; + valMask = softpipe->depth_stencil->stencil[face].valuemask; assert(ps); /* shouldn't get here if there's no stencil buffer */ diff --git a/src/gallium/drivers/trace/tr_state.c b/src/gallium/drivers/trace/tr_state.c index 546231612fb..8b147a8d377 100644 --- a/src/gallium/drivers/trace/tr_state.c +++ b/src/gallium/drivers/trace/tr_state.c @@ -281,8 +281,8 @@ void trace_dump_depth_stencil_alpha_state(const struct pipe_depth_stencil_alpha_ trace_dump_member(uint, &state->stencil[i], zpass_op); trace_dump_member(uint, &state->stencil[i], zfail_op); trace_dump_member(uint, &state->stencil[i], ref_value); - trace_dump_member(uint, &state->stencil[i], value_mask); - trace_dump_member(uint, &state->stencil[i], write_mask); + trace_dump_member(uint, &state->stencil[i], valuemask); + trace_dump_member(uint, &state->stencil[i], writemask); trace_dump_struct_end(); trace_dump_elem_end(); } diff --git a/src/gallium/include/pipe/p_state.h b/src/gallium/include/pipe/p_state.h index 46f62abf3fa..0a0ca770da8 100644 --- a/src/gallium/include/pipe/p_state.h +++ b/src/gallium/include/pipe/p_state.h @@ -188,9 +188,9 @@ struct pipe_stencil_state unsigned fail_op:3; /**< PIPE_STENCIL_OP_x */ unsigned zpass_op:3; /**< PIPE_STENCIL_OP_x */ unsigned zfail_op:3; /**< PIPE_STENCIL_OP_x */ - ubyte ref_value; - ubyte value_mask; - ubyte write_mask; + ubyte ref_value; + ubyte valuemask; + ubyte writemask; }; diff --git a/src/gallium/state_trackers/g3dvl/vl_context.c b/src/gallium/state_trackers/g3dvl/vl_context.c index fbea1363d87..c4c4e23c157 100644 --- a/src/gallium/state_trackers/g3dvl/vl_context.c +++ b/src/gallium/state_trackers/g3dvl/vl_context.c @@ -81,8 +81,8 @@ static int vlInitCommon(struct vlContext *context) dsa.stencil[i].zpass_op = PIPE_STENCIL_OP_KEEP; dsa.stencil[i].zfail_op = PIPE_STENCIL_OP_KEEP; dsa.stencil[i].ref_value = 0; - dsa.stencil[i].value_mask = 0; - dsa.stencil[i].write_mask = 0; + dsa.stencil[i].valuemask = 0; + dsa.stencil[i].writemask = 0; } dsa.alpha.enabled = 0; dsa.alpha.func = PIPE_FUNC_ALWAYS; diff --git a/src/mesa/state_tracker/st_atom_depth.c b/src/mesa/state_tracker/st_atom_depth.c index 0e791ceb208..8b5f22d0efe 100644 --- a/src/mesa/state_tracker/st_atom_depth.c +++ b/src/mesa/state_tracker/st_atom_depth.c @@ -112,8 +112,8 @@ update_depth_stencil_alpha(struct st_context *st) dsa->stencil[0].zfail_op = gl_stencil_op_to_pipe(st->ctx->Stencil.ZFailFunc[0]); dsa->stencil[0].zpass_op = gl_stencil_op_to_pipe(st->ctx->Stencil.ZPassFunc[0]); dsa->stencil[0].ref_value = st->ctx->Stencil.Ref[0] & 0xff; - dsa->stencil[0].value_mask = st->ctx->Stencil.ValueMask[0] & 0xff; - dsa->stencil[0].write_mask = st->ctx->Stencil.WriteMask[0] & 0xff; + dsa->stencil[0].valuemask = st->ctx->Stencil.ValueMask[0] & 0xff; + dsa->stencil[0].writemask = st->ctx->Stencil.WriteMask[0] & 0xff; if (st->ctx->Stencil._TestTwoSide) { dsa->stencil[1].enabled = 1; @@ -122,8 +122,8 @@ update_depth_stencil_alpha(struct st_context *st) dsa->stencil[1].zfail_op = gl_stencil_op_to_pipe(st->ctx->Stencil.ZFailFunc[1]); dsa->stencil[1].zpass_op = gl_stencil_op_to_pipe(st->ctx->Stencil.ZPassFunc[1]); dsa->stencil[1].ref_value = st->ctx->Stencil.Ref[1] & 0xff; - dsa->stencil[1].value_mask = st->ctx->Stencil.ValueMask[1] & 0xff; - dsa->stencil[1].write_mask = st->ctx->Stencil.WriteMask[1] & 0xff; + dsa->stencil[1].valuemask = st->ctx->Stencil.ValueMask[1] & 0xff; + dsa->stencil[1].writemask = st->ctx->Stencil.WriteMask[1] & 0xff; } else { dsa->stencil[1] = dsa->stencil[0]; diff --git a/src/mesa/state_tracker/st_cb_clear.c b/src/mesa/state_tracker/st_cb_clear.c index fca1107d72e..668c3f9ebf4 100644 --- a/src/mesa/state_tracker/st_cb_clear.c +++ b/src/mesa/state_tracker/st_cb_clear.c @@ -287,8 +287,8 @@ clear_with_quad(GLcontext *ctx, depth_stencil.stencil[0].zpass_op = PIPE_STENCIL_OP_REPLACE; depth_stencil.stencil[0].zfail_op = PIPE_STENCIL_OP_REPLACE; depth_stencil.stencil[0].ref_value = ctx->Stencil.Clear; - depth_stencil.stencil[0].value_mask = 0xff; - depth_stencil.stencil[0].write_mask = ctx->Stencil.WriteMask[0] & 0xff; + depth_stencil.stencil[0].valuemask = 0xff; + depth_stencil.stencil[0].writemask = ctx->Stencil.WriteMask[0] & 0xff; } cso_set_depth_stencil_alpha(st->cso_context, &depth_stencil);