From: lkcl <lkcl@web>
Date: Sun, 23 Apr 2023 12:55:21 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a7edf3898c4ebeeef7d4686957400753e9118df9;p=libreriscv.git

---

diff --git a/openpower/sv/sprs.mdwn b/openpower/sv/sprs.mdwn
index 5c6920acc..17c4a99e0 100644
--- a/openpower/sv/sprs.mdwn
+++ b/openpower/sv/sprs.mdwn
@@ -167,7 +167,9 @@ batches
 neither Register Hazards nor Memory Hazards inter-element exist
 (but inter-group definitely does).  This makes
 implementation far easier on resources because the Hazard Dependencies are
-effectively at a much coarser granularity than a single register.*
+effectively at a much coarser granularity than a single register.
+With element-width overrides extending down to the byte level reducing Dependency
+Hazard hardware complexity becomes even more important.*
 
 `hphint` may legitimately be set greater than `MAXVL`. This indicates to Multi-Issue
 hardware that even though MAXVL is relatively small the batches are *still independent*