From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 25 May 2020 21:21:10 +0000 (-0700)
Subject: Merge pull request #2078 from YosysHQ/eddie/xilinx_sim_tidy
X-Git-Tag: working-ls180~537
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a7f2ef6d34c4b336a910b3c6f3d2cc11da8a82b4;p=yosys.git

Merge pull request #2078 from YosysHQ/eddie/xilinx_sim_tidy

xilinx: tidy up cells_sim.v a little
---

a7f2ef6d34c4b336a910b3c6f3d2cc11da8a82b4