From: Gabe Black Date: Tue, 12 Jun 2007 16:21:47 +0000 (+0000) Subject: Make microOp vs microop and macroOp vs macroop capitilization consistent. X-Git-Tag: m5_2.0_beta4~359^2~9 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a7f3bbcfab9d54387517c2a52e56bfefee092901;p=gem5.git Make microOp vs microop and macroOp vs macroop capitilization consistent. src/arch/x86/isa/macroop.isa: Make microOp vs microop and macroOp vs macroop capitilization consistent. Also fill out the emulation environment handling a little more, and use an object to pass around output code. src/arch/x86/isa/microops/base.isa: Make microOp vs microop and macroOp vs macroop capitilization consistent. Also adjust python to C++ bool translation. --HG-- extra : convert_revision : 6f4bacfa334c42732c845f9a7f211cbefc73f96f --- diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa index e19016bd0..caf5bb8ce 100644 --- a/src/arch/sparc/isa/formats/mem/blockmem.isa +++ b/src/arch/sparc/isa/formats/mem/blockmem.isa @@ -248,14 +248,14 @@ def template BlockMemConstructor {{ : %(base_class)s("%(mnemonic)s", machInst) { %(constructor)s; - microOps[0] = new %(class_name)s_0(machInst); - microOps[1] = new %(class_name)s_1(machInst); - microOps[2] = new %(class_name)s_2(machInst); - microOps[3] = new %(class_name)s_3(machInst); - microOps[4] = new %(class_name)s_4(machInst); - microOps[5] = new %(class_name)s_5(machInst); - microOps[6] = new %(class_name)s_6(machInst); - microOps[7] = new %(class_name)s_7(machInst); + microops[0] = new %(class_name)s_0(machInst); + microops[1] = new %(class_name)s_1(machInst); + microops[2] = new %(class_name)s_2(machInst); + microops[3] = new %(class_name)s_3(machInst); + microops[4] = new %(class_name)s_4(machInst); + microops[5] = new %(class_name)s_5(machInst); + microops[6] = new %(class_name)s_6(machInst); + microops[7] = new %(class_name)s_7(machInst); } }}; @@ -289,9 +289,9 @@ let {{ for microPc in range(8): flag_code = '' if (microPc == 7): - flag_code = "flags[IsLastMicroOp] = true;" + flag_code = "flags[IsLastMicroop] = true;" elif (microPc == 0): - flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroOp] = true;" + flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroop] = true;" else: flag_code = "flags[IsDelayedCommit] = true;" pcedCode = matcher.sub("Frd_%d" % microPc, code) diff --git a/src/arch/sparc/isa/formats/micro.isa b/src/arch/sparc/isa/formats/micro.isa index da0f97d1b..c1d0c4f36 100644 --- a/src/arch/sparc/isa/formats/micro.isa +++ b/src/arch/sparc/isa/formats/micro.isa @@ -58,33 +58,33 @@ output header {{ class SparcMacroInst : public SparcStaticInst { protected: - const uint32_t numMicroOps; + const uint32_t numMicroops; //Constructor. SparcMacroInst(const char *mnem, ExtMachInst _machInst, - OpClass __opClass, uint32_t _numMicroOps) + OpClass __opClass, uint32_t _numMicroops) : SparcStaticInst(mnem, _machInst, __opClass), - numMicroOps(_numMicroOps) + numMicroops(_numMicroops) { - assert(numMicroOps); - microOps = new StaticInstPtr[numMicroOps]; - flags[IsMacroOp] = true; + assert(numMicroops); + microops = new StaticInstPtr[numMicroops]; + flags[IsMacroop] = true; } ~SparcMacroInst() { - delete [] microOps; + delete [] microops; } std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; - StaticInstPtr * microOps; + StaticInstPtr * microops; - StaticInstPtr fetchMicroOp(MicroPC microPC) + StaticInstPtr fetchMicroop(MicroPC microPC) { - assert(microPC < numMicroOps); - return microOps[microPC]; + assert(microPC < numMicroops); + return microops[microPC]; } %(MacroExecute)s @@ -100,7 +100,7 @@ output header {{ ExtMachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass) { - flags[IsMicroOp] = true; + flags[IsMicroop] = true; } }; diff --git a/src/arch/x86/isa/macroop.isa b/src/arch/x86/isa/macroop.isa index a7477c5a6..bc7fc8015 100644 --- a/src/arch/x86/isa/macroop.isa +++ b/src/arch/x86/isa/macroop.isa @@ -72,33 +72,33 @@ def template MacroExecPanic {{ output header {{ // Base class for combinationally generated macroops - class MacroOp : public StaticInst + class Macroop : public StaticInst { protected: - const uint32_t numMicroOps; + const uint32_t numMicroops; //Constructor. - MacroOp(const char *mnem, ExtMachInst _machInst, - uint32_t _numMicroOps) + Macroop(const char *mnem, ExtMachInst _machInst, + uint32_t _numMicroops) : StaticInst(mnem, _machInst, No_OpClass), - numMicroOps(_numMicroOps) + numMicroops(_numMicroops) { - assert(numMicroOps); - microOps = new StaticInstPtr[numMicroOps]; - flags[IsMacroOp] = true; + assert(numMicroops); + microops = new StaticInstPtr[numMicroops]; + flags[IsMacroop] = true; } - ~MacroOp() + ~Macroop() { - delete [] microOps; + delete [] microops; } - StaticInstPtr * microOps; + StaticInstPtr * microops; - StaticInstPtr fetchMicroOp(MicroPC microPC) + StaticInstPtr fetchMicroop(MicroPC microPC) { - assert(microPC < numMicroOps); - return microOps[microPC]; + assert(microPC < numMicroops); + return microops[microPC]; } std::string generateDisassembly(Addr pc, @@ -113,7 +113,7 @@ output header {{ // Basic instruction class declaration template. def template MacroDeclare {{ - namespace X86Microop + namespace X86Macroop { /** * Static instruction class for "%(mnemonic)s". @@ -122,20 +122,20 @@ def template MacroDeclare {{ { public: // Constructor. - %(class_name)s(ExtMachInst machInst); + %(class_name)s(ExtMachInst machInst, EmulEnv env); }; }; }}; // Basic instruction class constructor template. def template MacroConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst) - : %(base_class)s("%(mnemonic)s", machInst, %(num_micro_ops)s) + inline X86Macroop::%(class_name)s::%(class_name)s(ExtMachInst machInst, EmulEnv env) + : %(base_class)s("%(mnemonic)s", machInst, %(num_microops)s) { %(constructor)s; - //alloc_micro_ops is the code that sets up the microOps + //alloc_microops is the code that sets up the microops //array in the parent class. - %(alloc_micro_ops)s; + %(alloc_microops)s; } }}; @@ -153,7 +153,7 @@ let {{ } self.declared = False def getAllocator(self, env): - return "new X86Macroop::%s(machInst)" % self.name + return "new X86Macroop::%s(machInst, %s)" % (self.name, env.getAllocator()) def getDeclaration(self): #FIXME This first parameter should be the mnemonic. I need to #write some code which pulls that out @@ -167,14 +167,14 @@ let {{ micropc = 0 for op in self.microops: allocMicroops += \ - "microOps[%d] = %s;\n" % \ + "microops[%d] = %s;\n" % \ (micropc, op.getAllocator(True, False, micropc == 0, micropc == numMicroops - 1)) micropc += 1 iop = InstObjParams(self.name, self.name, "Macroop", - {"code" : "", "num_micro_ops" : numMicroops, - "alloc_micro_ops" : allocMicroops}) + {"code" : "", "num_microops" : numMicroops, + "alloc_microops" : allocMicroops}) return MacroConstructor.subst(iop); }}; @@ -201,26 +201,46 @@ output header {{ let {{ class EmulEnv(object): def __init__(self): - self.reg = "Not specified" - self.regm = "Not specified" + self.reg = "0" + self.regUsed = False + self.regm = "0" + self.regmUsed = False self.immediate = "IMMEDIATE" self.displacement = "DISPLACEMENT" self.addressSize = "ADDRSIZE" self.dataSize = "OPSIZE" def getAllocator(self): - return "EmulEmv(%(reg)s, %(regm)s, %(immediate)s, %(displacement)s, %(addressSize)s, %(dataSize)s)" % \ - self.__dict__() + return '''EmulEnv(%(reg)s, + %(regm)s, + %(immediate)s, + %(displacement)s, + %(addressSize)s, + %(dataSize)s)''' % \ + self.__dict__ + def addReg(self, reg): + print "Adding reg \"%s\"" % reg + if not self.regUsed: + print "Added as reg" + self.reg = reg + self.regUsed = True + elif not self.regmUsed: + print "Added as regm" + self.regm = reg + self.regmUsed = True + else: + raise Exception, "EmulEnv is out of register specialization spots." }}; let {{ def genMacroop(Name, env): + blocks = OutputBlocks() if not macroopDict.has_key(Name): raise Exception, "Unrecognized instruction: %s" % Name macroop = macroopDict[Name] if not macroop.declared: - global header_output - global decoder_output - header_output = macroop.getDeclaration() - decoder_output = macroop.getDefinition() - return "return %s;\n" % macroop.getAllocator(env) + blocks.header_output = macroop.getDeclaration() + blocks.decoder_output = macroop.getDefinition() + macroop.declared = True + blocks.decode_block = "return %s;\n" % macroop.getAllocator(env) + return blocks }}; diff --git a/src/arch/x86/isa/microops/base.isa b/src/arch/x86/isa/microops/base.isa index 7fa4f0457..a066d4802 100644 --- a/src/arch/x86/isa/microops/base.isa +++ b/src/arch/x86/isa/microops/base.isa @@ -64,14 +64,14 @@ let {{ //A class which is the base of all x86 micro ops. It provides a function to //set necessary flags appropriately. output header {{ - class X86MicroOpBase : public X86StaticInst + class X86MicroopBase : public X86StaticInst { protected: const char * instMnem; uint8_t opSize; uint8_t addrSize; - X86MicroOpBase(ExtMachInst _machInst, + X86MicroopBase(ExtMachInst _machInst, const char *mnem, const char *_instMnem, bool isMicro, bool isDelayed, bool isFirst, bool isLast, @@ -79,10 +79,10 @@ output header {{ X86StaticInst(mnem, _machInst, __opClass), instMnem(_instMnem) { - flags[IsMicroOp] = isMicro; + flags[IsMicroop] = isMicro; flags[IsDelayedCommit] = isDelayed; - flags[IsFirstMicroOp] = isFirst; - flags[IsLastMicroOp] = isLast; + flags[IsFirstMicroop] = isFirst; + flags[IsLastMicroop] = isLast; } std::string generateDisassembly(Addr pc, @@ -108,15 +108,19 @@ let {{ def __init__(self, name): self.name = name + # This converts a python bool into a C++ bool + def cppBool(self, val): + if val: + return "true" + else: + return "false" + # This converts a list of python bools into # a comma seperated list of C++ bools. def microFlagsText(self, vals): text = "" for val in vals: - if val: - text += ", true" - else: - text += ", false" + text += ", %s" % self.cppBool(val) return text def getAllocator(self, mnemonic, *microFlags): @@ -130,7 +134,7 @@ let {{ ////////////////////////////////////////////////////////////////////////// def template MicroLdStOpDeclare {{ - class %(class_name)s : public X86MicroOpBase + class %(class_name)s : public X86MicroopBase { protected: const uint8_t scale; diff --git a/src/arch/x86/isa/microops/limmop.isa b/src/arch/x86/isa/microops/limmop.isa index 5fce37126..a25d2b712 100644 --- a/src/arch/x86/isa/microops/limmop.isa +++ b/src/arch/x86/isa/microops/limmop.isa @@ -72,7 +72,7 @@ def template MicroLimmOpExecute {{ }}; def template MicroLimmOpDeclare {{ - class %(class_name)s : public X86MicroOpBase + class %(class_name)s : public X86MicroopBase { protected: const RegIndex dest; @@ -141,7 +141,7 @@ let {{ let {{ # Build up the all register version of this micro op - iop = InstObjParams("limm", "Limm", 'X86MicroOpBase', + iop = InstObjParams("limm", "Limm", 'X86MicroopBase', {"code" : "DestReg = imm;"}) header_output += MicroLimmOpDeclare.subst(iop) decoder_output += MicroLimmOpConstructor.subst(iop) diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index 52c13231c..c2aa27b67 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -231,17 +231,18 @@ let {{ self.ext = 0 def getAllocator(self, *microFlags): - allocator = '''new %(class_name)s(machInst, %(mnemonic)s, - %(flags)s %(src1)s, %(src2)s, %(dest)s, + allocator = '''new %(class_name)s(machInst, "%(mnemonic)s" + %(flags)s, %(src1)s, %(src2)s, %(dest)s, %(setStatus)s, %(dataSize)s, %(ext)s)''' % { "class_name" : self.className, "mnemonic" : self.mnemonic, "flags" : self.microFlagsText(microFlags), "src1" : self.src1, "src2" : self.src2, "dest" : self.dest, - "setStatus" : self.setStatus, + "setStatus" : self.cppBool(self.setStatus), "dataSize" : self.dataSize, "ext" : self.ext} + return allocator class RegOpImm(X86Microop): def __init__(self, dest, src1, imm): @@ -253,17 +254,18 @@ let {{ self.ext = 0 def getAllocator(self, *microFlags): - allocator = '''new %(class_name)s(machInst, %(mnemonic)s, - %(flags)s %(src1)s, %(imm8)s, %(dest)s, + allocator = '''new %(class_name)s(machInst, "%(mnemonic)s" + %(flags)s, %(src1)s, %(imm8)s, %(dest)s, %(setStatus)s, %(dataSize)s, %(ext)s)''' % { "class_name" : self.className, "mnemonic" : self.mnemonic, "flags" : self.microFlagsText(microFlags), "src1" : self.src1, "imm8" : self.imm8, "dest" : self.dest, - "setStatus" : self.setStatus, + "setStatus" : self.cppBool(self.setStatus), "dataSize" : self.dataSize, "ext" : self.ext} + return allocator }}; let {{ @@ -290,7 +292,7 @@ let {{ immCode = matcher.sub("imm8", code) # Build up the all register version of this micro op - iop = InstObjParams(name, Name, 'X86MicroOpBase', {"code" : regCode}) + iop = InstObjParams(name, Name, 'X86MicroopBase', {"code" : regCode}) header_output += MicroRegOpDeclare.subst(iop) decoder_output += MicroRegOpConstructor.subst(iop) exec_output += MicroRegOpExecute.subst(iop) @@ -305,7 +307,7 @@ let {{ # Build up the immediate version of this micro op iop = InstObjParams(name + "i", Name, - 'X86MicroOpBase', {"code" : immCode}) + 'X86MicroopBase', {"code" : immCode}) header_output += MicroRegOpImmDeclare.subst(iop) decoder_output += MicroRegOpImmConstructor.subst(iop) exec_output += MicroRegOpImmExecute.subst(iop) diff --git a/src/arch/x86/isa/microops/specop.isa b/src/arch/x86/isa/microops/specop.isa index a3ca7d91c..96fdf1c5e 100644 --- a/src/arch/x86/isa/microops/specop.isa +++ b/src/arch/x86/isa/microops/specop.isa @@ -69,7 +69,7 @@ def template MicroFaultExecute {{ }}; def template MicroFaultDeclare {{ - class %(class_name)s : public X86MicroOpBase + class %(class_name)s : public X86MicroopBase { protected: Fault fault; @@ -118,7 +118,7 @@ def template MicroFaultConstructor {{ let {{ # This microop takes in a single parameter, a fault to return. - iop = InstObjParams("fault", "GenFault", 'X86MicroOpBase', {"code" : ""}) + iop = InstObjParams("fault", "GenFault", 'X86MicroopBase', {"code" : ""}) header_output += MicroFaultDeclare.subst(iop) decoder_output += MicroFaultConstructor.subst(iop) exec_output += MicroFaultExecute.subst(iop) diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc index 3e2b0f03e..75792fa8c 100644 --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@ -162,7 +162,7 @@ Trace::InstRecord::dump() static int fd = 0; //Don't print what happens for each micro-op, just print out //once at the last op, and for regular instructions. - if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) + if(!staticInst->isMicroop() || staticInst->isLastMicroop()) { if(!cosim_listener) { @@ -245,7 +245,7 @@ Trace::InstRecord::dump() #if 0 //THE_ISA == SPARC_ISA //Don't print what happens for each micro-op, just print out //once at the last op, and for regular instructions. - if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) + if(!staticInst->isMicroop() || staticInst->isLastMicroop()) { static uint64_t regs[32] = { 0, 0, 0, 0, 0, 0, 0, 0, @@ -432,7 +432,7 @@ Trace::InstRecord::dump() setupSharedData(); // We took a trap on a micro-op... - if (wasMicro && !staticInst->isMicroOp()) + if (wasMicro && !staticInst->isMicroop()) { // let's skip comparing this tick while (!compared) @@ -444,13 +444,13 @@ Trace::InstRecord::dump() wasMicro = false; } - if (staticInst->isLastMicroOp()) + if (staticInst->isLastMicroop()) wasMicro = false; - else if (staticInst->isMicroOp()) + else if (staticInst->isMicroop()) wasMicro = true; - if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) { + if(!staticInst->isMicroop() || staticInst->isLastMicroop()) { while (!compared) { if (shared_data->flags == OWN_M5) { m5Pc = PC & TheISA::PAddrImplMask; diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index fab537748..ea1c7d87f 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -540,8 +540,8 @@ AtomicSimpleCPU::tick() } // @todo remove me after debugging with legion done - if (curStaticInst && (!curStaticInst->isMicroOp() || - curStaticInst->isFirstMicroOp())) + if (curStaticInst && (!curStaticInst->isMicroop() || + curStaticInst->isFirstMicroop())) instCnt++; if (simulate_stalls) { diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 33c5877a5..b4371b2c4 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -400,17 +400,17 @@ BaseSimpleCPU::preExecute() //If we decoded an instruction and it's microcoded, start pulling //out micro ops - if (instPtr && instPtr->isMacroOp()) { + if (instPtr && instPtr->isMacroop()) { curMacroStaticInst = instPtr; curStaticInst = curMacroStaticInst-> - fetchMicroOp(thread->readMicroPC()); + fetchMicroop(thread->readMicroPC()); } else { curStaticInst = instPtr; } } else { //Read the next micro op from the macro op curStaticInst = curMacroStaticInst-> - fetchMicroOp(thread->readMicroPC()); + fetchMicroop(thread->readMicroPC()); } //If we decoded an instruction this "tick", record information about it. @@ -475,7 +475,7 @@ BaseSimpleCPU::advancePC(Fault fault) thread->setNextMicroPC(1); } else { //If we're at the last micro op for this instruction - if (curStaticInst && curStaticInst->isLastMicroOp()) { + if (curStaticInst && curStaticInst->isLastMicroop()) { //We should be working with a macro op assert(curMacroStaticInst); //Close out this macro op, and clean up the diff --git a/src/cpu/static_inst.cc b/src/cpu/static_inst.cc index 64fcc0580..a5580d707 100644 --- a/src/cpu/static_inst.cc +++ b/src/cpu/static_inst.cc @@ -76,9 +76,9 @@ StaticInst::hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const } StaticInstPtr -StaticInst::fetchMicroOp(MicroPC micropc) +StaticInst::fetchMicroop(MicroPC micropc) { - panic("StaticInst::fetchMicroOp() called on instruction " + panic("StaticInst::fetchMicroop() called on instruction " "that is not microcoded."); } diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh index a58ac85d6..b11e74c6e 100644 --- a/src/cpu/static_inst.hh +++ b/src/cpu/static_inst.hh @@ -143,11 +143,11 @@ class StaticInstBase : public RefCounted IsUnverifiable, ///< Can't be verified by a checker //Flags for microcode - IsMacroOp, ///< Is a macroop containing microops - IsMicroOp, ///< Is a microop + IsMacroop, ///< Is a macroop containing microops + IsMicroop, ///< Is a microop IsDelayedCommit, ///< This microop doesn't commit right away - IsLastMicroOp, ///< This microop ends a microop sequence - IsFirstMicroOp, ///< This microop begins a microop sequence + IsLastMicroop, ///< This microop ends a microop sequence + IsFirstMicroop, ///< This microop begins a microop sequence //This flag doesn't do anything yet IsMicroBranch, ///< This microop branches within the microcode for a macroop @@ -242,11 +242,11 @@ class StaticInstBase : public RefCounted bool isQuiesce() const { return flags[IsQuiesce]; } bool isIprAccess() const { return flags[IsIprAccess]; } bool isUnverifiable() const { return flags[IsUnverifiable]; } - bool isMacroOp() const { return flags[IsMacroOp]; } - bool isMicroOp() const { return flags[IsMicroOp]; } + bool isMacroop() const { return flags[IsMacroop]; } + bool isMicroop() const { return flags[IsMicroop]; } bool isDelayedCommit() const { return flags[IsDelayedCommit]; } - bool isLastMicroOp() const { return flags[IsLastMicroOp]; } - bool isFirstMicroOp() const { return flags[IsFirstMicroOp]; } + bool isLastMicroop() const { return flags[IsLastMicroop]; } + bool isFirstMicroop() const { return flags[IsFirstMicroop]; } //This flag doesn't do anything yet bool isMicroBranch() const { return flags[IsMicroBranch]; } //@} @@ -369,7 +369,7 @@ class StaticInst : public StaticInstBase * Return the microop that goes with a particular micropc. This should * only be defined/used in macroops which will contain microops */ - virtual StaticInstPtr fetchMicroOp(MicroPC micropc); + virtual StaticInstPtr fetchMicroop(MicroPC micropc); /** * Return the target address for a PC-relative branch.