From: Cesar Strauss <cestrauss@gmail.com>
Date: Wed, 26 Oct 2022 22:02:21 +0000 (-0300)
Subject: Reset req_l latch on system reset
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a814ce2456e7d1f3b7ae40ad6e014a509dbd1130;p=soc.git

Reset req_l latch on system reset

Even if the holding register of SRLatch is really reset-less, it is still
reset at startup, because the latch reset port has reset=1. But, this only
works if the latch reset port is driven by the sync domain. In case of
req_l, it's driven by the comb domain, so the latch is not reset on system
reset.

Generate a pulse on system reset, and combine it with the latch reset.
---

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index 7eef2047..23ef36ea 100644
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -182,6 +182,10 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
             rw_domain = m.d.sync
         else:
             rw_domain = m.d.comb
+        # generate a pulse on system reset, to reset any latches, if needed
+        system_reset = Signal(reset=1)
+        m.d.sync += system_reset.eq(0)
+
         # add the ALU to the MultiCompUnit only if it is a "real" ALU
         # see AllFunctionUnits as to why: a FunctionUnitBaseMulti
         # only has one "real" ALU but multiple pseudo front-ends,
@@ -263,7 +267,8 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
 
         # dest operand latch (not using issue_i)
         rw_domain += req_l.s.eq(alu_pulsem & self.wrmask)
-        m.d.comb += req_l.r.eq(reset_w | prev_wr_go)
+        m.d.comb += req_l.r.eq(reset_w | prev_wr_go |
+                               Repl(system_reset, self.n_dst))
 
         # pass operation to the ALU (sync: plenty time to wait for src reads)
         op = self.get_op()