From: lkcl <lkcl@web>
Date: Tue, 7 Sep 2021 16:06:56 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~193
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a841025d56a364e2a495cfdab8ed164d684ed549;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 914595e8d..a808fa637 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -494,7 +494,7 @@ on SVP64.
 
 This mode merges common CR testing with predication, saving on instruction
 count. Below is the pseudocode excluding predicate zeroing and elwidth
-overrides.
+overrides. Note that the paeudocode for [[sv/cr_ops]] is slightly different.
 
     for i in range(VL):
         # predication test, skip all masked out elements.