From: Alan Lawrence Date: Wed, 3 Dec 2014 12:12:07 +0000 (+0000) Subject: [AArch64] Remove/merge redundant iterators X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a844a6958395311c579a982d82958088b418be77;p=gcc.git [AArch64] Remove/merge redundant iterators * config/aarch64/aarch64-simd.md (aarch64_simd_dup, orn3, bic3, add3, sub3, neg2, abs2, and3, ior3, xor3, one_cmpl2, aarch64_simd_lshr ,arch64_simd_ashr, aarch64_simd_imm_shl, aarch64_simd_reg_sshl, aarch64_simd_reg_shl_unsigned, aarch64_simd_reg_shr_signed, ashl3, lshr3, ashr3, vashl3, reduc_plus_scal_, aarch64_vcond_internal, vcondu, aarch64_cm, aarch64_cmtst): Change VDQ to VDQ_I. (mul3): Change VDQM to VDQ_BHSI. (aarch64_simd_vec_set,vashr3, vlshr3, vec_set, aarch64_mla, aarch64_mls, 3, aarch64_h): Change VQ_S to VDQ_BHSI. (*aarch64_mlal, *aarch64_mlsl, aarch64_l, aarch64_w, aarch64_shll_n): Change VDW to VD_BHSI. (*aarch64_combinez, *aarch64_combinez_be): Change VDIC to VD_BHSI. * config/aarch64/aarch64-simd-builtins.def (saddl, uaddl, ssubl, usubl, saddw, uaddw, ssubw, usubw, shadd, uhadd, srhadd, urhadd, sshll_n, ushll_n): Change BUILTIN_VDW to BUILTIN_VD_BHSI. * config/aarch64/iterators.md (SDQ_I, VDQ, VQ_S, VSDQ_I_BHSI, VDQM, VDW, VDIC, VDQQHS): Remove. (Vwtype): Update comment (changing VDW to VD_BHSI). From-SVN: r218310 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 75b935b2e4b..b688d82b2a8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,36 @@ +2014-12-03 Alan Lawrence + + * config/aarch64/aarch64-simd.md (aarch64_simd_dup, orn3, + bic3, add3, sub3, neg2, abs2, and3, + ior3, xor3, one_cmpl2, + aarch64_simd_lshr ,arch64_simd_ashr, + aarch64_simd_imm_shl, aarch64_simd_reg_sshl, + aarch64_simd_reg_shl_unsigned, aarch64_simd_reg_shr_signed, + ashl3, lshr3, ashr3, vashl3, + reduc_plus_scal_, aarch64_vcond_internal, + vcondu, aarch64_cm, aarch64_cmtst): + Change VDQ to VDQ_I. + + (mul3): Change VDQM to VDQ_BHSI. + (aarch64_simd_vec_set,vashr3, vlshr3, vec_set, + aarch64_mla, aarch64_mls, 3, + aarch64_h): Change VQ_S to VDQ_BHSI. + + (*aarch64_mlal, *aarch64_mlsl, + aarch64_l, + aarch64_w, aarch64_shll_n): + Change VDW to VD_BHSI. + (*aarch64_combinez, *aarch64_combinez_be): + Change VDIC to VD_BHSI. + + * config/aarch64/aarch64-simd-builtins.def (saddl, uaddl, ssubl, usubl, + saddw, uaddw, ssubw, usubw, shadd, uhadd, srhadd, urhadd, sshll_n, + ushll_n): Change BUILTIN_VDW to BUILTIN_VD_BHSI. + + * config/aarch64/iterators.md (SDQ_I, VDQ, VQ_S, VSDQ_I_BHSI, VDQM, VDW, + VDIC, VDQQHS): Remove. + (Vwtype): Update comment (changing VDW to VD_BHSI). + 2014-12-03 Richard Biener PR middle-end/14541 diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index 936b671163d..4eb70ff629f 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -114,20 +114,20 @@ BUILTIN_VQW (BINOP, ssubw2, 0) BUILTIN_VQW (BINOP, usubw2, 0) /* Implemented by aarch64_l. */ - BUILTIN_VDW (BINOP, saddl, 0) - BUILTIN_VDW (BINOP, uaddl, 0) - BUILTIN_VDW (BINOP, ssubl, 0) - BUILTIN_VDW (BINOP, usubl, 0) + BUILTIN_VD_BHSI (BINOP, saddl, 0) + BUILTIN_VD_BHSI (BINOP, uaddl, 0) + BUILTIN_VD_BHSI (BINOP, ssubl, 0) + BUILTIN_VD_BHSI (BINOP, usubl, 0) /* Implemented by aarch64_w. */ - BUILTIN_VDW (BINOP, saddw, 0) - BUILTIN_VDW (BINOP, uaddw, 0) - BUILTIN_VDW (BINOP, ssubw, 0) - BUILTIN_VDW (BINOP, usubw, 0) + BUILTIN_VD_BHSI (BINOP, saddw, 0) + BUILTIN_VD_BHSI (BINOP, uaddw, 0) + BUILTIN_VD_BHSI (BINOP, ssubw, 0) + BUILTIN_VD_BHSI (BINOP, usubw, 0) /* Implemented by aarch64_h. */ - BUILTIN_VQ_S (BINOP, shadd, 0) - BUILTIN_VQ_S (BINOP, uhadd, 0) - BUILTIN_VQ_S (BINOP, srhadd, 0) - BUILTIN_VQ_S (BINOP, urhadd, 0) + BUILTIN_VDQ_BHSI (BINOP, shadd, 0) + BUILTIN_VDQ_BHSI (BINOP, uhadd, 0) + BUILTIN_VDQ_BHSI (BINOP, srhadd, 0) + BUILTIN_VDQ_BHSI (BINOP, urhadd, 0) /* Implemented by aarch64_hn. */ BUILTIN_VQN (BINOP, addhn, 0) BUILTIN_VQN (BINOP, raddhn, 0) @@ -202,8 +202,8 @@ BUILTIN_VSDQ_I_DI (SHIFTACC, srsra_n, 0) BUILTIN_VSDQ_I_DI (USHIFTACC, ursra_n, 0) /* Implemented by aarch64_shll_n. */ - BUILTIN_VDW (SHIFTIMM, sshll_n, 0) - BUILTIN_VDW (USHIFTIMM, ushll_n, 0) + BUILTIN_VD_BHSI (SHIFTIMM, sshll_n, 0) + BUILTIN_VD_BHSI (USHIFTIMM, ushll_n, 0) /* Implemented by aarch64_shll2_n. */ BUILTIN_VQW (SHIFTIMM, sshll2_n, 0) BUILTIN_VQW (SHIFTIMM, ushll2_n, 0) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 8e31456381f..0ec132345a5 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -42,8 +42,9 @@ }) (define_insn "aarch64_simd_dup" - [(set (match_operand:VDQ 0 "register_operand" "=w, w") - (vec_duplicate:VDQ (match_operand: 1 "register_operand" "r, w")))] + [(set (match_operand:VDQ_I 0 "register_operand" "=w, w") + (vec_duplicate:VDQ_I + (match_operand: 1 "register_operand" "r, w")))] "TARGET_SIMD" "@ dup\\t%0., %1 @@ -242,45 +243,45 @@ ]) (define_insn "orn3" - [(set (match_operand:VDQ 0 "register_operand" "=w") - (ior:VDQ (not:VDQ (match_operand:VDQ 1 "register_operand" "w")) - (match_operand:VDQ 2 "register_operand" "w")))] + [(set (match_operand:VDQ_I 0 "register_operand" "=w") + (ior:VDQ_I (not:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")) + (match_operand:VDQ_I 2 "register_operand" "w")))] "TARGET_SIMD" "orn\t%0., %2., %1." [(set_attr "type" "neon_logic")] ) (define_insn "bic3" - [(set (match_operand:VDQ 0 "register_operand" "=w") - (and:VDQ (not:VDQ (match_operand:VDQ 1 "register_operand" "w")) - (match_operand:VDQ 2 "register_operand" "w")))] + [(set (match_operand:VDQ_I 0 "register_operand" "=w") + (and:VDQ_I (not:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")) + (match_operand:VDQ_I 2 "register_operand" "w")))] "TARGET_SIMD" "bic\t%0., %2., %1." [(set_attr "type" "neon_logic")] ) (define_insn "add3" - [(set (match_operand:VDQ 0 "register_operand" "=w") - (plus:VDQ (match_operand:VDQ 1 "register_operand" "w") - (match_operand:VDQ 2 "register_operand" "w")))] + [(set (match_operand:VDQ_I 0 "register_operand" "=w") + (plus:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w") + (match_operand:VDQ_I 2 "register_operand" "w")))] "TARGET_SIMD" "add\t%0., %1., %2." [(set_attr "type" "neon_add")] ) (define_insn "sub3" - [(set (match_operand:VDQ 0 "register_operand" "=w") - (minus:VDQ (match_operand:VDQ 1 "register_operand" "w") - (match_operand:VDQ 2 "register_operand" "w")))] + [(set (match_operand:VDQ_I 0 "register_operand" "=w") + (minus:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w") + (match_operand:VDQ_I 2 "register_operand" "w")))] "TARGET_SIMD" "sub\t%0., %1., %2." [(set_attr "type" "neon_sub")] ) (define_insn "mul3" - [(set (match_operand:VDQM 0 "register_operand" "=w") - (mult:VDQM (match_operand:VDQM 1 "register_operand" "w") - (match_operand:VDQM 2 "register_operand" "w")))] + [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w") + (mult:VDQ_BHSI (match_operand:VDQ_BHSI 1 "register_operand" "w") + (match_operand:VDQ_BHSI 2 "register_operand" "w")))] "TARGET_SIMD" "mul\t%0., %1., %2." [(set_attr "type" "neon_mul_")] @@ -377,16 +378,16 @@ ) (define_insn "neg2" - [(set (match_operand:VDQ 0 "register_operand" "=w") - (neg:VDQ (match_operand:VDQ 1 "register_operand" "w")))] + [(set (match_operand:VDQ_I 0 "register_operand" "=w") + (neg:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")))] "TARGET_SIMD" "neg\t%0., %1." [(set_attr "type" "neon_neg")] ) (define_insn "abs2" - [(set (match_operand:VDQ 0 "register_operand" "=w") - (abs:VDQ (match_operand:VDQ 1 "register_operand" "w")))] + [(set (match_operand:VDQ_I 0 "register_operand" "=w") + (abs:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")))] "TARGET_SIMD" "abs\t%0., %1." [(set_attr "type" "neon_abs")] @@ -434,46 +435,46 @@ ) (define_insn "and3" - [(set (match_operand:VDQ 0 "register_operand" "=w") - (and:VDQ (match_operand:VDQ 1 "register_operand" "w") - (match_operand:VDQ 2 "register_operand" "w")))] + [(set (match_operand:VDQ_I 0 "register_operand" "=w") + (and:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w") + (match_operand:VDQ_I 2 "register_operand" "w")))] "TARGET_SIMD" "and\t%0., %1., %2." [(set_attr "type" "neon_logic")] ) (define_insn "ior3" - [(set (match_operand:VDQ 0 "register_operand" "=w") - (ior:VDQ (match_operand:VDQ 1 "register_operand" "w") - (match_operand:VDQ 2 "register_operand" "w")))] + [(set (match_operand:VDQ_I 0 "register_operand" "=w") + (ior:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w") + (match_operand:VDQ_I 2 "register_operand" "w")))] "TARGET_SIMD" "orr\t%0., %1., %2." [(set_attr "type" "neon_logic")] ) (define_insn "xor3" - [(set (match_operand:VDQ 0 "register_operand" "=w") - (xor:VDQ (match_operand:VDQ 1 "register_operand" "w") - (match_operand:VDQ 2 "register_operand" "w")))] + [(set (match_operand:VDQ_I 0 "register_operand" "=w") + (xor:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w") + (match_operand:VDQ_I 2 "register_operand" "w")))] "TARGET_SIMD" "eor\t%0., %1., %2." [(set_attr "type" "neon_logic")] ) (define_insn "one_cmpl2" - [(set (match_operand:VDQ 0 "register_operand" "=w") - (not:VDQ (match_operand:VDQ 1 "register_operand" "w")))] + [(set (match_operand:VDQ_I 0 "register_operand" "=w") + (not:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")))] "TARGET_SIMD" "not\t%0., %1." [(set_attr "type" "neon_logic")] ) (define_insn "aarch64_simd_vec_set" - [(set (match_operand:VQ_S 0 "register_operand" "=w,w,w") - (vec_merge:VQ_S - (vec_duplicate:VQ_S + [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w,w,w") + (vec_merge:VDQ_BHSI + (vec_duplicate:VDQ_BHSI (match_operand: 1 "aarch64_simd_general_operand" "r,w,Utv")) - (match_operand:VQ_S 3 "register_operand" "0,0,0") + (match_operand:VDQ_BHSI 3 "register_operand" "0,0,0") (match_operand:SI 2 "immediate_operand" "i,i,i")))] "TARGET_SIMD" { @@ -495,45 +496,45 @@ ) (define_insn "aarch64_simd_lshr" - [(set (match_operand:VDQ 0 "register_operand" "=w") - (lshiftrt:VDQ (match_operand:VDQ 1 "register_operand" "w") - (match_operand:VDQ 2 "aarch64_simd_rshift_imm" "Dr")))] + [(set (match_operand:VDQ_I 0 "register_operand" "=w") + (lshiftrt:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w") + (match_operand:VDQ_I 2 "aarch64_simd_rshift_imm" "Dr")))] "TARGET_SIMD" "ushr\t%0., %1., %2" [(set_attr "type" "neon_shift_imm")] ) (define_insn "aarch64_simd_ashr" - [(set (match_operand:VDQ 0 "register_operand" "=w") - (ashiftrt:VDQ (match_operand:VDQ 1 "register_operand" "w") - (match_operand:VDQ 2 "aarch64_simd_rshift_imm" "Dr")))] + [(set (match_operand:VDQ_I 0 "register_operand" "=w") + (ashiftrt:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w") + (match_operand:VDQ_I 2 "aarch64_simd_rshift_imm" "Dr")))] "TARGET_SIMD" "sshr\t%0., %1., %2" [(set_attr "type" "neon_shift_imm")] ) (define_insn "aarch64_simd_imm_shl" - [(set (match_operand:VDQ 0 "register_operand" "=w") - (ashift:VDQ (match_operand:VDQ 1 "register_operand" "w") - (match_operand:VDQ 2 "aarch64_simd_lshift_imm" "Dl")))] + [(set (match_operand:VDQ_I 0 "register_operand" "=w") + (ashift:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w") + (match_operand:VDQ_I 2 "aarch64_simd_lshift_imm" "Dl")))] "TARGET_SIMD" "shl\t%0., %1., %2" [(set_attr "type" "neon_shift_imm")] ) (define_insn "aarch64_simd_reg_sshl" - [(set (match_operand:VDQ 0 "register_operand" "=w") - (ashift:VDQ (match_operand:VDQ 1 "register_operand" "w") - (match_operand:VDQ 2 "register_operand" "w")))] + [(set (match_operand:VDQ_I 0 "register_operand" "=w") + (ashift:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w") + (match_operand:VDQ_I 2 "register_operand" "w")))] "TARGET_SIMD" "sshl\t%0., %1., %2." [(set_attr "type" "neon_shift_reg")] ) (define_insn "aarch64_simd_reg_shl_unsigned" - [(set (match_operand:VDQ 0 "register_operand" "=w") - (unspec:VDQ [(match_operand:VDQ 1 "register_operand" "w") - (match_operand:VDQ 2 "register_operand" "w")] + [(set (match_operand:VDQ_I 0 "register_operand" "=w") + (unspec:VDQ_I [(match_operand:VDQ_I 1 "register_operand" "w") + (match_operand:VDQ_I 2 "register_operand" "w")] UNSPEC_ASHIFT_UNSIGNED))] "TARGET_SIMD" "ushl\t%0., %1., %2." @@ -541,9 +542,9 @@ ) (define_insn "aarch64_simd_reg_shl_signed" - [(set (match_operand:VDQ 0 "register_operand" "=w") - (unspec:VDQ [(match_operand:VDQ 1 "register_operand" "w") - (match_operand:VDQ 2 "register_operand" "w")] + [(set (match_operand:VDQ_I 0 "register_operand" "=w") + (unspec:VDQ_I [(match_operand:VDQ_I 1 "register_operand" "w") + (match_operand:VDQ_I 2 "register_operand" "w")] UNSPEC_ASHIFT_SIGNED))] "TARGET_SIMD" "sshl\t%0., %1., %2." @@ -551,8 +552,8 @@ ) (define_expand "ashl3" - [(match_operand:VDQ 0 "register_operand" "") - (match_operand:VDQ 1 "register_operand" "") + [(match_operand:VDQ_I 0 "register_operand" "") + (match_operand:VDQ_I 1 "register_operand" "") (match_operand:SI 2 "general_operand" "")] "TARGET_SIMD" { @@ -598,8 +599,8 @@ ) (define_expand "lshr3" - [(match_operand:VDQ 0 "register_operand" "") - (match_operand:VDQ 1 "register_operand" "") + [(match_operand:VDQ_I 0 "register_operand" "") + (match_operand:VDQ_I 1 "register_operand" "") (match_operand:SI 2 "general_operand" "")] "TARGET_SIMD" { @@ -645,8 +646,8 @@ ) (define_expand "ashr3" - [(match_operand:VDQ 0 "register_operand" "") - (match_operand:VDQ 1 "register_operand" "") + [(match_operand:VDQ_I 0 "register_operand" "") + (match_operand:VDQ_I 1 "register_operand" "") (match_operand:SI 2 "general_operand" "")] "TARGET_SIMD" { @@ -692,9 +693,9 @@ ) (define_expand "vashl3" - [(match_operand:VDQ 0 "register_operand" "") - (match_operand:VDQ 1 "register_operand" "") - (match_operand:VDQ 2 "register_operand" "")] + [(match_operand:VDQ_I 0 "register_operand" "") + (match_operand:VDQ_I 1 "register_operand" "") + (match_operand:VDQ_I 2 "register_operand" "")] "TARGET_SIMD" { emit_insn (gen_aarch64_simd_reg_sshl (operands[0], operands[1], @@ -702,13 +703,13 @@ DONE; }) -;; Using mode VQ_S as there is no V2DImode neg! +;; Using mode VDQ_BHSI as there is no V2DImode neg! ;; Negating individual lanes most certainly offsets the ;; gain from vectorization. (define_expand "vashr3" - [(match_operand:VQ_S 0 "register_operand" "") - (match_operand:VQ_S 1 "register_operand" "") - (match_operand:VQ_S 2 "register_operand" "")] + [(match_operand:VDQ_BHSI 0 "register_operand" "") + (match_operand:VDQ_BHSI 1 "register_operand" "") + (match_operand:VDQ_BHSI 2 "register_operand" "")] "TARGET_SIMD" { rtx neg = gen_reg_rtx (mode); @@ -745,9 +746,9 @@ ) (define_expand "vlshr3" - [(match_operand:VQ_S 0 "register_operand" "") - (match_operand:VQ_S 1 "register_operand" "") - (match_operand:VQ_S 2 "register_operand" "")] + [(match_operand:VDQ_BHSI 0 "register_operand" "") + (match_operand:VDQ_BHSI 1 "register_operand" "") + (match_operand:VDQ_BHSI 2 "register_operand" "")] "TARGET_SIMD" { rtx neg = gen_reg_rtx (mode); @@ -783,7 +784,7 @@ ) (define_expand "vec_set" - [(match_operand:VQ_S 0 "register_operand") + [(match_operand:VDQ_BHSI 0 "register_operand") (match_operand: 1 "register_operand") (match_operand:SI 2 "immediate_operand")] "TARGET_SIMD" @@ -879,10 +880,11 @@ (define_insn "aarch64_mla" - [(set (match_operand:VQ_S 0 "register_operand" "=w") - (plus:VQ_S (mult:VQ_S (match_operand:VQ_S 2 "register_operand" "w") - (match_operand:VQ_S 3 "register_operand" "w")) - (match_operand:VQ_S 1 "register_operand" "0")))] + [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w") + (plus:VDQ_BHSI (mult:VDQ_BHSI + (match_operand:VDQ_BHSI 2 "register_operand" "w") + (match_operand:VDQ_BHSI 3 "register_operand" "w")) + (match_operand:VDQ_BHSI 1 "register_operand" "0")))] "TARGET_SIMD" "mla\t%0., %2., %3." [(set_attr "type" "neon_mla_")] @@ -926,10 +928,10 @@ ) (define_insn "aarch64_mls" - [(set (match_operand:VQ_S 0 "register_operand" "=w") - (minus:VQ_S (match_operand:VQ_S 1 "register_operand" "0") - (mult:VQ_S (match_operand:VQ_S 2 "register_operand" "w") - (match_operand:VQ_S 3 "register_operand" "w"))))] + [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w") + (minus:VDQ_BHSI (match_operand:VDQ_BHSI 1 "register_operand" "0") + (mult:VDQ_BHSI (match_operand:VDQ_BHSI 2 "register_operand" "w") + (match_operand:VDQ_BHSI 3 "register_operand" "w"))))] "TARGET_SIMD" "mls\t%0., %2., %3." [(set_attr "type" "neon_mla_")] @@ -974,9 +976,9 @@ ;; Max/Min operations. (define_insn "3" - [(set (match_operand:VQ_S 0 "register_operand" "=w") - (MAXMIN:VQ_S (match_operand:VQ_S 1 "register_operand" "w") - (match_operand:VQ_S 2 "register_operand" "w")))] + [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w") + (MAXMIN:VDQ_BHSI (match_operand:VDQ_BHSI 1 "register_operand" "w") + (match_operand:VDQ_BHSI 2 "register_operand" "w")))] "TARGET_SIMD" "\t%0., %1., %2." [(set_attr "type" "neon_minmax")] @@ -1314,9 +1316,9 @@ (plus: (mult: (ANY_EXTEND: - (match_operand:VDW 1 "register_operand" "w")) + (match_operand:VD_BHSI 1 "register_operand" "w")) (ANY_EXTEND: - (match_operand:VDW 2 "register_operand" "w"))) + (match_operand:VD_BHSI 2 "register_operand" "w"))) (match_operand: 3 "register_operand" "0")))] "TARGET_SIMD" "mlal\t%0., %1., %2." @@ -1329,9 +1331,9 @@ (match_operand: 1 "register_operand" "0") (mult: (ANY_EXTEND: - (match_operand:VDW 2 "register_operand" "w")) + (match_operand:VD_BHSI 2 "register_operand" "w")) (ANY_EXTEND: - (match_operand:VDW 3 "register_operand" "w")))))] + (match_operand:VD_BHSI 3 "register_operand" "w")))))] "TARGET_SIMD" "mlsl\t%0., %2., %3." [(set_attr "type" "neon_mla__long")] @@ -1826,7 +1828,7 @@ (define_expand "reduc_plus_scal_" [(match_operand: 0 "register_operand" "=w") - (unspec:VDQ [(match_operand:VDQ 1 "register_operand" "w")] + (unspec:VDQ_I [(match_operand:VDQ_I 1 "register_operand" "w")] UNSPEC_ADDV)] "TARGET_SIMD" { @@ -2033,13 +2035,13 @@ }) (define_expand "aarch64_vcond_internal" - [(set (match_operand:VDQ 0 "register_operand") - (if_then_else:VDQ + [(set (match_operand:VDQ_I 0 "register_operand") + (if_then_else:VDQ_I (match_operator 3 "comparison_operator" - [(match_operand:VDQ 4 "register_operand") - (match_operand:VDQ 5 "nonmemory_operand")]) - (match_operand:VDQ 1 "nonmemory_operand") - (match_operand:VDQ 2 "nonmemory_operand")))] + [(match_operand:VDQ_I 4 "register_operand") + (match_operand:VDQ_I 5 "nonmemory_operand")]) + (match_operand:VDQ_I 1 "nonmemory_operand") + (match_operand:VDQ_I 2 "nonmemory_operand")))] "TARGET_SIMD" { rtx op1 = operands[1]; @@ -2374,13 +2376,13 @@ }) (define_expand "vcondu" - [(set (match_operand:VDQ 0 "register_operand") - (if_then_else:VDQ + [(set (match_operand:VDQ_I 0 "register_operand") + (if_then_else:VDQ_I (match_operator 3 "comparison_operator" - [(match_operand:VDQ 4 "register_operand") - (match_operand:VDQ 5 "nonmemory_operand")]) - (match_operand:VDQ 1 "nonmemory_operand") - (match_operand:VDQ 2 "nonmemory_operand")))] + [(match_operand:VDQ_I 4 "register_operand") + (match_operand:VDQ_I 5 "nonmemory_operand")]) + (match_operand:VDQ_I 1 "nonmemory_operand") + (match_operand:VDQ_I 2 "nonmemory_operand")))] "TARGET_SIMD" { emit_insn (gen_aarch64_vcond_internal (operands[0], operands[1], @@ -2476,8 +2478,8 @@ (define_insn "*aarch64_combinez" [(set (match_operand: 0 "register_operand" "=&w") (vec_concat: - (match_operand:VDIC 1 "register_operand" "w") - (match_operand:VDIC 2 "aarch64_simd_imm_zero" "Dz")))] + (match_operand:VD_BHSI 1 "register_operand" "w") + (match_operand:VD_BHSI 2 "aarch64_simd_imm_zero" "Dz")))] "TARGET_SIMD && !BYTES_BIG_ENDIAN" "mov\\t%0.8b, %1.8b" [(set_attr "type" "neon_move")] @@ -2486,8 +2488,8 @@ (define_insn "*aarch64_combinez_be" [(set (match_operand: 0 "register_operand" "=&w") (vec_concat: - (match_operand:VDIC 2 "aarch64_simd_imm_zero" "Dz") - (match_operand:VDIC 1 "register_operand" "w")))] + (match_operand:VD_BHSI 2 "aarch64_simd_imm_zero" "Dz") + (match_operand:VD_BHSI 1 "register_operand" "w")))] "TARGET_SIMD && BYTES_BIG_ENDIAN" "mov\\t%0.8b, %1.8b" [(set_attr "type" "neon_move")] @@ -2626,9 +2628,9 @@ (define_insn "aarch64_l" [(set (match_operand: 0 "register_operand" "=w") (ADDSUB: (ANY_EXTEND: - (match_operand:VDW 1 "register_operand" "w")) + (match_operand:VD_BHSI 1 "register_operand" "w")) (ANY_EXTEND: - (match_operand:VDW 2 "register_operand" "w"))))] + (match_operand:VD_BHSI 2 "register_operand" "w"))))] "TARGET_SIMD" "l\t%0., %1., %2." [(set_attr "type" "neon__long")] @@ -2640,7 +2642,7 @@ [(set (match_operand: 0 "register_operand" "=w") (ADDSUB: (match_operand: 1 "register_operand" "w") (ANY_EXTEND: - (match_operand:VDW 2 "register_operand" "w"))))] + (match_operand:VD_BHSI 2 "register_operand" "w"))))] "TARGET_SIMD" "w\\t%0., %1., %2." [(set_attr "type" "neon__widen")] @@ -2710,9 +2712,9 @@ ;; h. (define_insn "aarch64_h" - [(set (match_operand:VQ_S 0 "register_operand" "=w") - (unspec:VQ_S [(match_operand:VQ_S 1 "register_operand" "w") - (match_operand:VQ_S 2 "register_operand" "w")] + [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w") + (unspec:VDQ_BHSI [(match_operand:VDQ_BHSI 1 "register_operand" "w") + (match_operand:VDQ_BHSI 2 "register_operand" "w")] HADDSUB))] "TARGET_SIMD" "h\\t%0., %1., %2." @@ -3519,7 +3521,7 @@ (define_insn "aarch64_shll_n" [(set (match_operand: 0 "register_operand" "=w") - (unspec: [(match_operand:VDW 1 "register_operand" "w") + (unspec: [(match_operand:VD_BHSI 1 "register_operand" "w") (match_operand:SI 2 "aarch64_simd_shift_imm_bitsize_" "i")] VSHLL))] @@ -3633,8 +3635,8 @@ [(set (match_operand: 0 "register_operand" "=w,w") (neg: (COMPARISONS: - (match_operand:VDQ 1 "register_operand" "w,w") - (match_operand:VDQ 2 "aarch64_simd_reg_or_zero" "w,ZDz") + (match_operand:VDQ_I 1 "register_operand" "w,w") + (match_operand:VDQ_I 2 "aarch64_simd_reg_or_zero" "w,ZDz") )))] "TARGET_SIMD" "@ @@ -3698,8 +3700,8 @@ [(set (match_operand: 0 "register_operand" "=w") (neg: (UCOMPARISONS: - (match_operand:VDQ 1 "register_operand" "w") - (match_operand:VDQ 2 "register_operand" "w") + (match_operand:VDQ_I 1 "register_operand" "w") + (match_operand:VDQ_I 2 "register_operand" "w") )))] "TARGET_SIMD" "cm\t%0, %, %" @@ -3765,10 +3767,10 @@ [(set (match_operand: 0 "register_operand" "=w") (plus: (eq: - (and:VDQ - (match_operand:VDQ 1 "register_operand" "w") - (match_operand:VDQ 2 "register_operand" "w")) - (match_operand:VDQ 3 "aarch64_simd_imm_zero")) + (and:VDQ_I + (match_operand:VDQ_I 1 "register_operand" "w") + (match_operand:VDQ_I 2 "register_operand" "w")) + (match_operand:VDQ_I 3 "aarch64_simd_imm_zero")) (match_operand: 4 "aarch64_simd_imm_minus_one"))) ] "TARGET_SIMD" diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 8b9ff98ba12..76be6927eb2 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -32,18 +32,12 @@ ;; Iterator for all integer modes (up to 64-bit) (define_mode_iterator ALLI [QI HI SI DI]) -;; Iterator scalar modes (up to 64-bit) -(define_mode_iterator SDQ_I [QI HI SI DI]) - ;; Iterator for all integer modes that can be extended (up to 64-bit) (define_mode_iterator ALLX [QI HI SI]) ;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes) (define_mode_iterator GPF [SF DF]) -;; Integer vector modes. -(define_mode_iterator VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V2DI]) - ;; Integer vector modes. (define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI]) @@ -72,16 +66,6 @@ ;; Quad vector with only 2 element modes. (define_mode_iterator VQ_2E [V2DI V2DF]) -;; All vector modes, except double. -(define_mode_iterator VQ_S [V8QI V16QI V4HI V8HI V2SI V4SI]) - -;; Vector and scalar, 64 & 128-bit container: all vector integer mode; -;; 8, 16, 32-bit scalar integer modes -(define_mode_iterator VSDQ_I_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI]) - -;; Vector modes for moves. -(define_mode_iterator VDQM [V8QI V16QI V4HI V8HI V2SI V4SI]) - ;; This mode iterator allows :P to be used for patterns that operate on ;; addresses in different modes. In LP64, only DI will match, while in ;; ILP32, either can match. @@ -132,9 +116,6 @@ ;; All quad integer narrow-able modes. (define_mode_iterator VQN [V8HI V4SI V2DI]) -;; All double integer widen-able modes. -(define_mode_iterator VDW [V8QI V4HI V2SI]) - ;; Vector and scalar 128-bit container: narrowable 16, 32, 64-bit integer modes (define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI]) @@ -144,9 +125,6 @@ ;; Double vector modes for combines. (define_mode_iterator VDC [V8QI V4HI V2SI V2SF DI DF]) -;; Double vector modes for combines. -(define_mode_iterator VDIC [V8QI V4HI V2SI]) - ;; Vector modes except double int. (define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF]) @@ -159,9 +137,6 @@ ;; Vector modes for H, S and D types. (define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI]) -;; Vector modes for Q, H and S types. -(define_mode_iterator VDQQHS [V8QI V16QI V4HI V8HI V2SI V4SI]) - ;; Vector and scalar integer modes for H and S (define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI]) @@ -487,7 +462,7 @@ ) -;; Widened mode register suffixes for VDW/VQW. +;; Widened mode register suffixes for VD_BHSI/VQW. (define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s") (V2SI "2d") (V16QI "8h") (V8HI "4s") (V4SI "2d")])