From: lkcl <lkcl@web>
Date: Fri, 4 Jun 2021 17:06:17 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~799
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a84b234bca6bdcfc20e8403443f1506e4eddfd40;p=libreriscv.git

---

diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn
index d0bdf3261..ef561b80b 100644
--- a/openpower/sv/int_fp_mv.mdwn
+++ b/openpower/sv/int_fp_mv.mdwn
@@ -109,11 +109,19 @@ TODO: review and investigate other language semantics
 
 # Proposed New Scalar Instructions
 
-All of the following instructions use the standard OpenPower conversion to/from 64-bit float format when reading/writing a 32-bit float from/to a FPR.
+All of the following instructions use the standard OpenPower conversion to/from 64-bit float format when reading/writing a 32-bit float from/to a FPR.  All integers however are sourced/stored in the *GPR*.
+
+Integer operands and results being in the GPR is the key differentiator between the proposed instructions
+(the entire rationale) compated to existing Scalar Power ISA.
+All existing Power ISA Scalar conversion instructions, all
+operands are FPRs, even if the format of the source or destination
+data is actually a scalar integer.
 
 Note that source and destination widths can be overridden by SimpleV
 SVP64, and that SVP64 also has Saturation Modes *in addition*
-to those independently described here.  The interactions with SVP64
+to those independently described here. SVP64 Overrides and Saturation
+work on *both* Fixed *and* Floating Point.
+ The interactions with SVP64
 are explained in the  [[int_fp_mv/appendix]]
 
 ## FPR to GPR moves