From: lkcl <lkcl@web>
Date: Fri, 21 Apr 2023 11:39:59 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a856aaca8603162301d2b66e65e9259fdc2a9c00;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls012.mdwn b/openpower/sv/rfc/ls012.mdwn
index 9bdf1c759..01b9dbe36 100644
--- a/openpower/sv/rfc/ls012.mdwn
+++ b/openpower/sv/rfc/ls012.mdwn
@@ -667,7 +667,7 @@ The key to headings and sections are as follows:
   instead.  see [[sv/po9_encoding]].
 * **Level** - Compliancy Subset and Simple-V Level. `SFFS` indicates "mandatory"
   in SFFS. All else is "optional" however some instructions are further Subsetted
-  within Simple-V.
+  within Simple-V: SV/Embedded, SV/DSP and SV/Supercomputing.
 * **regs** - a guide to register usage, to how costly Hazard Management
   will be, in hardware: