From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 17 Mar 2015 10:52:54 +0000 (+0100)
Subject: litescope: use CRG from Migen
X-Git-Tag: 24jan2021_ls180~2484
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a874f85854d5d102f6851be501444cdc02f3ae02;p=litex.git

litescope: use CRG from Migen
---

diff --git a/misoclib/tools/litescope/example_designs/targets/simple.py b/misoclib/tools/litescope/example_designs/targets/simple.py
index 8bb033db..22453901 100644
--- a/misoclib/tools/litescope/example_designs/targets/simple.py
+++ b/misoclib/tools/litescope/example_designs/targets/simple.py
@@ -1,4 +1,5 @@
 from migen.bank.description import *
+from migen.genlib.io import CRG
 
 from misoclib.soc import SoC
 from misoclib.tools.litescope.common import *
@@ -7,20 +8,6 @@ from misoclib.tools.litescope.frontend.io import LiteScopeIO
 from misoclib.tools.litescope.frontend.la import LiteScopeLA
 from misoclib.tools.litescope.core.port import LiteScopeTerm
 
-class _CRG(Module):
-	def __init__(self, clk_in):
-		self.clock_domains.cd_sys = ClockDomain()
-		self.clock_domains.cd_por = ClockDomain(reset_less=True)
-
-		# Power on Reset (vendor agnostic)
-		rst_n = Signal()
-		self.sync.por += rst_n.eq(1)
-		self.comb += [
-			self.cd_sys.clk.eq(clk_in),
-			self.cd_por.clk.eq(clk_in),
-			self.cd_sys.rst.eq(~rst_n)
-		]
-
 class LiteScopeSoC(SoC, AutoCSR):
 	csr_map = {
 		"io":	16,
@@ -37,8 +24,7 @@ class LiteScopeSoC(SoC, AutoCSR):
 			with_identifier=True,
 			with_timer=False
 		)
-		clk_in = platform.request(platform.default_clk_name)
-		self.submodules.crg = _CRG(clk_in if not hasattr(clk_in, "p") else clk_in.p)
+		self.submodules.crg = CRG(platform.request(platform.default_clk_name))
 
 		self.submodules.io = LiteScopeIO(8)
 		for i in range(8):