From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 22 May 2019 12:09:49 +0000 (+0100)
Subject: read-after-write self-referring hazard
X-Git-Tag: div_pipeline~1990
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a878168fb22776aa7a76f617255f5d88952782e6;p=soc.git

read-after-write self-referring hazard
---

diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py
index 2755842d..1c0caca0 100644
--- a/src/experiment/score6600.py
+++ b/src/experiment/score6600.py
@@ -390,12 +390,13 @@ def scoreboard_sim(dut, alusim):
 
         # create some instructions (some random, some regression tests)
         instrs = []
-        if True:
-            for i in range(5):
+        if False:
+            for i in range(10):
                 src1 = randint(1, dut.n_regs-1)
                 src2 = randint(1, dut.n_regs-1)
                 while True:
                     dest = randint(1, dut.n_regs-1)
+                    break
                     if dest not in [src1, src2]:
                         break
                 #src1 = 2
@@ -439,6 +440,34 @@ def scoreboard_sim(dut, alusim):
             instrs.append( (3, 6, 7, 2) )
             instrs.append( (4, 4, 7, 1) )
 
+        if False:
+            # self-read/write-after-write followed by Read-after-Write
+            instrs.append((1, 1, 1, 1))
+            instrs.append((1, 5, 3, 0))
+
+        if False:
+            # Read-after-Write followed by self-read-after-write
+            instrs.append((5, 6, 1, 2))
+            instrs.append((1, 1, 1, 1))
+
+        if False:
+            # self-read-write sandwich
+            instrs.append((5, 6, 1, 2))
+            instrs.append((1, 1, 1, 1))
+            instrs.append((1, 5, 3, 0))
+
+        if True:
+            instrs.append( (7, 1, 2, 0) )
+            instrs.append( (1, 1, 4, 2) )
+            instrs.append( (2, 3, 2, 2) )
+            instrs.append( (5, 3, 1, 0) )
+            instrs.append( (7, 3, 5, 2) )
+            instrs.append( (1, 2, 6, 2) )
+            instrs.append( (5, 2, 5, 2) )
+            instrs.append( (2, 2, 3, 0) )
+            instrs.append( (4, 2, 2, 1) )
+            instrs.append( (2, 4, 6, 1) )
+
         # issue instruction(s), wait for issue to be free before proceeding
         for i, (src1, src2, dest, op) in enumerate(instrs):
 
diff --git a/src/scoreboard/dependence_cell.py b/src/scoreboard/dependence_cell.py
index f509010c..9e3d8e92 100644
--- a/src/scoreboard/dependence_cell.py
+++ b/src/scoreboard/dependence_cell.py
@@ -129,10 +129,10 @@ class DependenceCell(Elaboratable):
                                   (self.dest_i & self.src2_i))
 
         # connect up hazard checks: read-after-write and write-after-read
+        m.d.comb += dest_c.hazard_i.eq(self.rd_pend_i) # read-after-write
         with m.If(~selfhazard):
-            m.d.comb += dest_c.hazard_i.eq(self.rd_pend_i) # read-after-write
-        m.d.comb += src1_c.hazard_i.eq(self.wr_pend_i) # write-after-read
-        m.d.comb += src2_c.hazard_i.eq(self.wr_pend_i) # write-after-read
+            m.d.comb += src1_c.hazard_i.eq(self.wr_pend_i) # write-after-read
+            m.d.comb += src2_c.hazard_i.eq(self.wr_pend_i) # write-after-read
 
         # connect fwd / reg-sel outputs
         for c, fwd, rsel in [(dest_c, self.dest_fwd_o, self.dest_rsel_o),
@@ -144,8 +144,8 @@ class DependenceCell(Elaboratable):
         # to be accumulated to indicate if register is in use (globally)
         # after ORing, is fed back in to rd_pend_i / wr_pend_i
         m.d.comb += self.rd_rsel_o.eq(src1_c.q_o | src2_c.q_o)
-        with m.If(~selfhazard):
-            m.d.comb += self.wr_rsel_o.eq(dest_c.q_o)
+        #with m.If(~selfhazard):
+        m.d.comb += self.wr_rsel_o.eq(dest_c.q_o)
 
         return m