From: Luke Kenneth Casson Leighton Date: Thu, 1 Aug 2019 01:23:10 +0000 (+0100) Subject: remove i_specfn and o_specfn from FP*MuxInOut, use self.alu.ispec() and ospec() X-Git-Tag: ls180-24jan2020~574 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a88acb92b232388a290fdd330c05ff65920438e7;p=ieee754fpu.git remove i_specfn and o_specfn from FP*MuxInOut, use self.alu.ispec() and ospec() every class has an alu object, the pipe specs are the same for all use-cases so.... --- diff --git a/src/ieee754/fclass/pipeline.py b/src/ieee754/fclass/pipeline.py index dbb4460a..204ef32e 100644 --- a/src/ieee754/fclass/pipeline.py +++ b/src/ieee754/fclass/pipeline.py @@ -67,12 +67,6 @@ class FPClassMuxInOutBase(ReservationStations): self.alu = pkls(self.in_pspec, self.out_pspec, modkls) ReservationStations.__init__(self, num_rows) - def i_specfn(self): - return FPBaseData(self.in_pspec) - - def o_specfn(self): - return FPPackData(self.out_pspec) - class FPClassMuxInOut(FPClassMuxInOutBase): """ Reservation-Station version of FPClass pipeline. diff --git a/src/ieee754/fcvt/pipeline.py b/src/ieee754/fcvt/pipeline.py index 2eb83c5a..a7b01f70 100644 --- a/src/ieee754/fcvt/pipeline.py +++ b/src/ieee754/fcvt/pipeline.py @@ -89,7 +89,7 @@ class FPCVTMuxInOutBase(ReservationStations): """ Reservation-Station version of FPCVT pipeline. * fan-in on inputs (an array of FPBaseData: a,b,mid) - * 2-stage multiplier pipeline + * converter pipeline (alu) * fan-out on outputs (an array of FPPackData: z,mid) Fan-in and Fan-out are combinatorial. @@ -106,12 +106,6 @@ class FPCVTMuxInOutBase(ReservationStations): self.alu = pkls(modkls, e_extra, self.in_pspec, self.out_pspec) ReservationStations.__init__(self, num_rows) - def i_specfn(self): - return FPBaseData(self.in_pspec) - - def o_specfn(self): - return FPPackData(self.out_pspec) - class FPCVTF2IntMuxInOut(FPCVTMuxInOutBase): """ Reservation-Station version of FPCVT pipeline. diff --git a/src/ieee754/fpadd/pipeline.py b/src/ieee754/fpadd/pipeline.py index bbeff3d1..43247417 100644 --- a/src/ieee754/fpadd/pipeline.py +++ b/src/ieee754/fpadd/pipeline.py @@ -89,9 +89,3 @@ class FPADDMuxInOut(ReservationStations): self.pspec = PipelineSpec(width, self.id_wid, op_wid) self.alu = FPADDBasePipe(self.pspec) ReservationStations.__init__(self, num_rows) - - def i_specfn(self): - return FPBaseData(self.pspec) - - def o_specfn(self): - return FPPackData(self.pspec) diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py index 3bbf3123..939447ac 100644 --- a/src/ieee754/fpdiv/pipeline.py +++ b/src/ieee754/fpdiv/pipeline.py @@ -188,9 +188,3 @@ class FPDIVMuxInOut(ReservationStations): # self.alu = FPDIVBasePipe(new_pspec) self.alu = FPDIVBasePipe(self.pspec) ReservationStations.__init__(self, num_rows) - - def i_specfn(self): - return FPBaseData(self.pspec) - - def o_specfn(self): - return FPPackData(self.pspec) diff --git a/src/ieee754/fpmul/pipeline.py b/src/ieee754/fpmul/pipeline.py index dae5fbb4..82b881ca 100644 --- a/src/ieee754/fpmul/pipeline.py +++ b/src/ieee754/fpmul/pipeline.py @@ -1,4 +1,7 @@ -"""IEEE Floating Point Multiplier Pipeline +"""IEEE754 Floating Point Multiplier Pipeline + +Copyright (C) 2019 Luke Kenneth Casson Leighton +Copyright (C) 2019 Jake Lifshay Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=77 @@ -86,9 +89,3 @@ class FPMULMuxInOut(ReservationStations): self.pspec = PipelineSpec(width, self.id_wid, self.op_wid) self.alu = FPMULBasePipe(self.pspec) ReservationStations.__init__(self, num_rows) - - def i_specfn(self): - return FPBaseData(self.pspec) - - def o_specfn(self): - return FPPackData(self.pspec) diff --git a/src/ieee754/fpmul/specialcases.py b/src/ieee754/fpmul/specialcases.py index efab2e32..4fc3e3cf 100644 --- a/src/ieee754/fpmul/specialcases.py +++ b/src/ieee754/fpmul/specialcases.py @@ -1,4 +1,9 @@ -# IEEE Floating Point Multiplier +"""IEEE754 Floating Point Multiplier + +Copyright (C) 2019 Luke Kenneth Casson Leighton +Copyright (C) 2019 Jake Lifshay + +""" from nmigen import Module, Signal, Cat, Const from nmigen.cli import main, verilog diff --git a/src/nmutil/concurrentunit.py b/src/nmutil/concurrentunit.py index 3d426ff9..a04f5769 100644 --- a/src/nmutil/concurrentunit.py +++ b/src/nmutil/concurrentunit.py @@ -4,7 +4,7 @@ * data goes through a pipeline * results fan back out. - the output data format has to have a member "mid", which is used + the output data format has to have a member "muxid", which is used as the array index on fan-out """ @@ -40,7 +40,8 @@ class ReservationStations(Elaboratable): Input: num_rows - number of input and output Reservation Stations - Requires: the addition of an "alu" object, an i_specfn and an o_specfn + Requires: the addition of an "alu" object, from which ispec and ospec + are taken, and inpipe and outpipe are connected to it * fan-in on inputs (an array of FPADDBaseData: a,b,mid) * ALU pipeline @@ -71,4 +72,8 @@ class ReservationStations(Elaboratable): def ports(self): return self._ports + def i_specfn(self): + return self.alu.ispec() + def o_specfn(self): + return self.alu.ospec() diff --git a/src/nmutil/stageapi.py b/src/nmutil/stageapi.py index 6ed34f5e..5c0308e2 100644 --- a/src/nmutil/stageapi.py +++ b/src/nmutil/stageapi.py @@ -158,11 +158,11 @@ class StageHelper(Stage): if stage is not None: self.set_specs(self, self) - def ospec(self, name): + def ospec(self, name=None): assert self._ospecfn is not None return _spec(self._ospecfn, name) - def ispec(self, name): + def ispec(self, name=None): assert self._ispecfn is not None return _spec(self._ispecfn, name)